QUANTUM DOT ARRAY DEVICES WITH METAL SOURCE AND DRAIN
First Claim
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1. A field effect transistor fabricated on a substrate, the field effect transistor (FET) comprising:
- a recessed metal gate formed in the substrate, the recessed metal gate including a gate dielectric and a metal gate electrode;
a metal source region at least partially embedded in the substrate, the metal source region having an enlarged contact area adjacent to a carrier reservoir; and
a metal drain region at least partially embedded in the substrate, the metal drain region having an enlarged contact area adjacent to a carrier reservoir; and
a channel region adjacent to the recessed metal gate and extending between the metal source region and the metal drain region.
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Abstract
Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.
76 Citations
21 Claims
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1. A field effect transistor fabricated on a substrate, the field effect transistor (FET) comprising:
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a recessed metal gate formed in the substrate, the recessed metal gate including a gate dielectric and a metal gate electrode; a metal source region at least partially embedded in the substrate, the metal source region having an enlarged contact area adjacent to a carrier reservoir; and a metal drain region at least partially embedded in the substrate, the metal drain region having an enlarged contact area adjacent to a carrier reservoir; and a channel region adjacent to the recessed metal gate and extending between the metal source region and the metal drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of controlling a number of charge carriers in a transistor channel, the method comprising:
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forming a transistor having source and drain regions that include doped charge carrier reservoirs for injection of charge into a three-dimensional conducting channel; and embedding metal quantum dots in the source and drain regions. - View Dependent Claims (12)
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13. A method of making a quantum dot transistor, the method comprising:
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forming doped silicon source and drain regions between a pair of isolation trenches in a silicon substrate; forming epitaxial channels; forming a gate that includes a gate dielectric having a high dielectric constant; and embedding metal quantum dots in the source and drain regions. - View Dependent Claims (14, 15, 16, 17)
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18. A transistor array layout, comprising:
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a first regular surface pattern of quantum dot array elements configured as transistor source and drain regions; and a second regular surface pattern of gate array elements interspersed alternately among the quantum dot array elements. - View Dependent Claims (19, 20, 21)
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Specification