THIN FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME

• US 20140084264A1
• Filed: 03/13/2013
• Published: 03/27/2014
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: LEE, Dae-Woo
• Granted Patent: US 8,994,027 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H10K 50/00 Organic light-emitting devices integrated devices or assemblies of multiple devices H10K59/00, H10K65/00; organic semiconductor lasers H01S5/36
• CPC Class Codes: H10K 59/10 OLED displays
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements

Abstract

A thin film transistor (TFT) array substrate includes a TFT including an active layer, a gate electrode, a source electrode, a drain electrode, a first gate insulating layer and a second gate insulating layer formed between the active layer and the gate electrode, and an interlayer insulating layer formed between the gate electrode and the source electrode and the drain electrode; a pixel electrode formed in an opening of the interlayer insulating layer, the pixel electrode including transparent conductive oxide; a translucent electrode formed in a region corresponding to the pixel electrode, between the first gate insulating layer and the second gate insulating layer; and a capacitor including a lower electrode formed from the same layer as the active layer, and an upper electrode formed from the same layer as the translucent electrode.

Claims

1. A thin film transistor (TFT) array substrate comprising:

a TFT comprising an active layer, a gate electrode, a source electrode, a drain electrode, a first gate insulating layer and a second gate insulating layer foamed between the active layer and the gate electrode, and an interlayer insulating layer formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode;

a pixel electrode formed in an opening of the interlayer insulating layer, the pixel electrode comprising a transparent conductive oxide;

a translucent electrode formed in a region corresponding to the pixel electrode, between the first gate insulating layer and the second gate insulating layer; and

a capacitor comprising a lower electrode formed from the same layer as the active layer, and an upper electrode formed from the same layer as the translucent electrode.

2. The TFT array substrate of claim 1, wherein the translucent electrode comprises a translucent metal layer.

3. The TFT array substrate of claim 2, wherein the translucent metal layer comprises silver (Ag) or an alloy comprising Ag.

4. The TFT array substrate of claim 2, wherein, in the translucent electrode, the translucent metal layer is interposed between layers comprising transparent conductive oxide.

5. The TFT array substrate of claim 1, wherein the transparent conductive oxide comprises at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

6. The TFT array substrate of claim 1, wherein the pixel electrode is formed from the same layer as the gate electrode.

7. The TFT array substrate of claim 1, wherein the gate electrode comprises a first layer comprising the transparent conductive oxide, and a second layer comprising metal having a resistance less than that of the first layer.

8. The TFT array substrate of claim 1, wherein the lower electrode of the capacitor comprises a semiconductor doped with an ion impurity.

9. The TFT array substrate of claim 8, wherein the upper electrode of the capacitor comprises a translucent metal layer.

10. The TFT array substrate of claim 1, wherein an opening is formed in the interlayer insulating layer corresponding to the upper electrode of the capacitor, and a planarization layer that covers the source electrode and the drain electrode contacts the second gate insulating layer through the opening.

11. An organic light-emitting display device comprising:

a thin film transistor (TFT) array substrate comprising;

a TFT comprising an active layer, a gate electrode, a source electrode, a drain electrode, a first gate insulating layer and a second gate insulating layer formed between the active layer and the gate electrode, and an interlayer insulating layer formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode;

a pixel electrode formed in an opening of the interlayer insulating layer, the pixel electrode comprising a transparent conductive oxide;

a translucent electrode formed in a region corresponding to the pixel electrode, between the first gate insulating layer and the second gate insulating layer; and

a capacitor comprising a lower electrode formed from the same layer as the active layer, and an upper electrode formed from the same layer as the translucent electrode;

an intermediate layer comprising an organic emission layer formed on the pixel electrode; and

a counter electrode formed on the intermediate layer.

12. The organic light-emitting display device of claim 11, wherein the counter electrode is a reflective electrode.

13. A method of manufacturing a thin film transistor (TFT) array substrate, the method comprising:

a first mask process for forming a semiconductor layer on a substrate, and patterning the semiconductor layer to form an active layer of a TFT and a lower electrode of a capacitor;

a second mask process for forming a first gate insulating layer, forming a translucent metal layer on the first gate insulating layer, and patterning the translucent metal layer to form a translucent electrode and an upper electrode of the capacitor;

a third mask process for forming a second gate insulating layer, forming on the second gate insulating layer a first layer comprising transparent conductive oxide and a second layer comprising metal, and patterning the first layer and the second layer to form a pixel electrode, a gate electrode, and a capacitor protection layer;

a fourth mask process for forming an interlayer insulating layer, and forming in the interlayer insulating layer openings for exposing the pixel electrode, a source region and a drain region of the active layer, and the capacitor protection layer; and

a fifth mask process for forming a metal layer, and patterning the metal layer to form a source electrode and a drain electrode.

14. The method of claim 13, wherein, in the second mask process, the translucent metal layer comprises silver (Ag) or an alloy comprising Ag.

15. The method of claim 13, wherein, in the second mask process, the translucent metal layer comprises a transparent conductive oxide.

16. The method of claim 13, wherein, after the third mask process is performed, the source region and the drain region of the active layer are doped with an ion impurity.

17. The method of claim 13, wherein, in the fifth mask process, the capacitor protection layer is removed.

18. The method of claim 17, wherein, after the capacitor protection layer is removed, the lower electrode is doped with an ion impurity.

19. The method of claim 15, wherein, in the fifth mask process, the second layer of the pixel electrode is removed together with the metal layer.

20. The method of claim 19, further comprising a sixth mask process for forming a planarization layer, and forming in the planarization layer an opening corresponding to the pixel electrode.