NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK
First Claim
1. A semiconductor device, comprising:
- a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, and further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body;
a source and drain material region disposed above the three-dimensional group III-V material body;
a trench disposed in the source and drain material region separating a source region from a drain region, the trench also partially disposed in the bottom barrier layer and completely exposing the channel region; and
a gate stack disposed in the trench and on and completely surrounding the channel region, the gate stack comprising;
a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region;
a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of the channel region; and
a gate electrode disposed on the second dielectric layer.
2 Assignments
0 Petitions
Accused Products
Abstract
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
21 Citations
36 Claims
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1. A semiconductor device, comprising:
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a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, and further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, the trench also partially disposed in the bottom barrier layer and completely exposing the channel region; and a gate stack disposed in the trench and on and completely surrounding the channel region, the gate stack comprising; a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of the channel region; and a gate electrode disposed on the second dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6)
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7-8. -8. (canceled)
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9. A semiconductor device, comprising:
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a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate; a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising; a first dielectric layer disposed on outer portions, but not an inner portion, of each of the channel regions; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of each of the channel regions; and a gate electrode disposed on the second dielectric layer; a bottom barrier layer disposed between the substrate and the bottom-most group III-V material nanowire, wherein a bottom portion of the gate stack is disposed on the bottom barrier layer; and source and drain regions surrounding portions of each of the group III-V material nanowires, on either side of the gate stack. - View Dependent Claims (10, 12, 13, 14, 15)
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11. (canceled)
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16. A semiconductor device, comprising:
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a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, and further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, the trench also partially disposed in the bottom barrier layer and completely exposing the channel region; and a gate stack disposed in the trench and on and completely surrounding the channel region, the gate stack comprising; a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region; a second, different, dielectric layer conformal with and disposed on the first dielectric layer, but not on the channel region; and a gate electrode disposed on the second dielectric layer. - View Dependent Claims (17, 18, 19, 20, 21)
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22-23. -23. (canceled)
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24. A semiconductor device, comprising:
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a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate; a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising; a first dielectric layer disposed on each of the channel regions; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the first dielectric layer, but not on each of the channel regions; and a gate electrode disposed on the second dielectric layer; and source and drain regions surrounding portions of each of the group III-V material nanowires, on either side of the gate stack. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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31. A semiconductor device, comprising:
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a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate; a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising; a first dielectric layer disposed on outer portions, but not an inner portion, of each of the channel regions; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of each of the channel regions; and a gate electrode disposed on the second dielectric layer; source and drain regions surrounding portions of each of the group III-V material nanowires, on either side of the gate stack; and a top barrier layer disposed between the source and drain regions and each of the group III-V material nanowires. - View Dependent Claims (32)
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33. A semiconductor device, comprising:
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a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region; and a gate stack disposed in the trench and on the exposed portion of the channel region, the gate stack comprising; a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region; a second, different, dielectric layer conformal with and disposed on the first dielectric layer, but not on the channel region, wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8; and a gate electrode disposed on the second dielectric layer. - View Dependent Claims (34)
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35. A semiconductor device, comprising:
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a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region; and a gate stack disposed in the trench and on the exposed portion of the channel region, the gate stack comprising; a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region; a second, different, dielectric layer conformal with and disposed on the first dielectric layer, but not on the channel region, wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer, and wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiOx), aluminum oxide (AlOx), hafnium oxide (HfO2), zirconium oxide (ZrO2), and lanthanum oxide (La2O3), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiOx), silicon oxynitride (SiON), silicon dioxide (SiO2) and silicon nitride (Si3N4); and a gate electrode disposed on the second dielectric layer. - View Dependent Claims (36)
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Specification