REPLACEMENT CHANNELS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME USING DOPANT CONCENTRATION BOOST

• US 20140084351A1
• Filed: 09/27/2012
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Yu-Lien, TSAI, Ming-Huan, WANN, Clement Hsingjen
• Granted Patent: US 8,946,035 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.

Claims

1. A method for forming a semiconductor transistor, said method comprising:

defining a channel region in a semiconductor substrate, said channel region associated with a transistor;

removing channel material from said channel region thereby forming a void in said semiconductor substrate in said channel region;

forming replacement channel material within said void, said replacement channel material comprising one of Ge and SiGe, and including a dopant, and having an as-deposited average dopant concentration less than a first dopant concentration; and

further doping said replacement channel material with said dopant thereby increasing said average dopant concentration to greater than said first dopant concentration.

2. The method as in claim 1, wherein said first dopant concentration is 5E18 atoms/cm³.

3. The method as in claim 1, wherein said channel material comprises a portion of said semiconductor substrate and said semiconductor substrate is silicon.

4. The method as in claim 1, wherein said further doping forms a gradient of dopant concentration in said replacement channel material such that an upper portion of said replacement channel material has a higher dopant concentration than a lower portion of said replacement channel material.

5. The method as in claim 1, wherein said removing channel material comprises one of dry etching and wet etching.

6. The method as in claim 1, wherein said forming replacement channel material comprises epitaxial deposition.

7. The method as in claim 1, wherein one of:

a) said semiconductor transistor is an NMOS transistor and said dopant comprises boron, and

b) said semiconductor transistor is a PMOS transistor and said dopant comprises phosphorus.

8. The method as in claim 1, wherein said further doping comprises beam line ion implantation.

9. The method as in claim 1, wherein said further doping comprises plasma doping (PLAD).

10. The method as in claim 1, wherein said further doping comprises one of beam line ion implantation and plasma doping and further comprising annealing after said further doping.

11. The method as in claim 1, wherein said defining a channel region comprises forming a dummy gate over a dummy gate dielectric then removing said dummy gate and said dummy gate dielectric to expose said channel region, and

further comprising forming a high-k gate dielectric over said replacement channel material and forming a metal transistor gate over said high-k gate dielectric material.

12. A method for forming a FinFET semiconductor device, said method comprising:

forming a fin over a substrate, at least a portion of said fin comprising a channel region and said fin formed of a semiconductor material;

removing channel material from said channel region thereby forming a void in said fin in said channel region;

forming replacement channel material within said void, said replacement channel material comprising one of Ge and SiGe, and including a dopant, and having an as-deposited average dopant concentration of less than 5E18 atoms/cm³; and

further doping said replacement channel material with said dopant thereby increasing said average dopant concentration to greater than 5E18 atoms/cm³.

13. The method as in claim 12, further comprising, prior to said removing channel material, forming a dummy gate over a dummy gate dielectric over said fin then removing said dummy gate and said dummy gate dielectric thereby defining said channel region, and further comprising forming a high-k gate dielectric over said replacement channel material and forming a metal gate over said high-k gate dielectric.

14. The method as in claim 12, wherein said semiconductor material comprises silicon and said further doping comprises one of beam line ion implantation and plasma doping, and

further comprising annealing said replacement channel material after said further doping.

15. A semiconductor transistor device comprising:

a substrate;

a channel comprising a channel material formed in an opening in said substrate, said channel material comprising one of Ge and SiGe, doped with a dopant material, said channel material including a dopant gradient in which an upper portion of said channel material has a higher dopant concentration than a lower portion of said channel material;

a transistor gate formed over said channel material; and

source/drain materials formed in source/drain openings in said substrate and adjacent said channel.

16. The semiconductor transistor device as in claim 15, further comprising a gate oxide between said channel and said transistor gate and wherein said substrate comprises a silicon wafer and said transistor gate is a metal gate.

17. The semiconductor transistor device as in claim 15, wherein said upper portion of said channel material has a dopant concentration greater than 5E18 atoms/cm³ and said lower portion of said channel material has a dopant concentration less than 5E18 atoms/cm³.

18. The semiconductor transistor device as in claim 15, wherein said semiconductor transistor is an NMOS transistor and said dopant material comprises boron.

19. The semiconductor transistor device as in claim 15, wherein said semiconductor transistor comprises a PMOS transistor and said dopant comprises phosphorus.

20. The semiconductor transistor device as in claim 15, wherein said semiconductor transistor device comprises a FinFET and said substrate comprises a semiconductor fin.