Semiconductor Device and Method for Manufacturing a Semiconductor Device

• US 20140084362A1
• Filed: 09/26/2012
• Published: 03/27/2014
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schloesser, Till, Zundel, Markus
• Granted Patent: US 9,941,403 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench.

Claims

1. A semiconductor device, comprising:

a transistor comprising a source region, a drain region, and a gate electrode, the gate electrode being disposed in a first trench arranged in a top surface of a semiconductor substrate; and

a control electrode disposed in a second trench arranged in the top surface of the semiconductor substrate, the second trench having a second shape that is different from a first shape of the first trench.

2. The semiconductor device according to claim 1, further comprising a field plate disposed below the gate electrode, and wherein no field plate is disposed below the control electrode.

3. The semiconductor device according to claim 1, wherein the source region is disposed adjacent to the top surface of the semiconductor substrate and the drain region is disposed at a back side of the semiconductor substrate, the semiconductor device further comprising a body region adjacent to the gate electrode and a drift zone disposed between the drain region and the body region.

4. The semiconductor device according to claim 3, further comprising a plurality of columns of differently doped portions arranged in the drift zone and extending vertically with respect to the top surface of the semiconductor substrate so that a superjunction device is formed.

5. The semiconductor device according to claim 1, wherein a lateral distance between the first and second trenches is selected so that a body region adjacent to the gate electrode is completely depleted when a voltage corresponding to a threshold voltage of the transistor is applied to the gate electrode.

6. The semiconductor device according to claim 1, wherein a distance between the first and second trenches is less than a depth of the first or second trench.

7. The semiconductor device according to claim 1, wherein the first trench has a greater depth than the second trench.

8. The semiconductor device according to claim 1, wherein the control electrode extends to a greater depth than a depth of the gate electrode, the depth being measured from the top surface of the semiconductor substrate.

9. A semiconductor device, comprising:

a plurality of transistor cells, each of the transistor cells comprising a source region, a drain region, and a gate electrode disposed in a trench arranged in a top surface of a semiconductor substrate;

wherein the gate electrodes of different transistor cells are electrically coupled to each other, the source regions of different transistor cells are electrically coupled to each other, and the drain regions of different transistor cells are electrically coupled to each other; and

wherein d≦

2*Wm is fulfilled for a lateral distance d between the trenches,

where Wm denotes a maximum width of a surface depletion region formed in the semiconductor substrate adjacent to the gate electrodes.

10. The semiconductor device of claim 9, wherein the plurality of transistor cells comprise first and second transistor cells, the first transistor cells comprising a first gate electrode, the second transistor cells comprising a second gate electrode, and wherein a shape of the first gate electrode is different from a shape of the second gate electrode.

11. The semiconductor device of claim 10, wherein the first gate electrode is disposed in a first trench and the second gate electrode is disposed in a second trench, the first trench having first dimensions different from second dimensions of the second trench.

12. The semiconductor device of claim 10, wherein the first gate electrode is disposed in a first trench and the second gate electrode is disposed in a second trench, a field plate is disposed in the first trench, and no field plate is disposed in the second trench.

13. The semiconductor device of claim 9, wherein a lateral distance between adjacent trenches is less than 120 nm.

14. A method of manufacturing a semiconductor device, comprising:

forming a transistor by forming a source region, a drain region, and a gate electrode, wherein the gate electrode is formed by forming a first trench in a top surface of the semiconductor substrate; and

forming a control electrode by forming a second trench in the top surface of the semiconductor substrate.

15. The method of claim 14, wherein the second trench is formed after the first trench is formed.

16. The method according to claim 15, wherein the second trench is formed in a self-aligned manner with respect to the first trench.

17. The method of claim 14, wherein the first trench is formed to have a greater depth than the second trench.

18. The method of claim 14, wherein the first and second trenches are formed to have a distance of less than 120 nm.

19. The method according to claim 17, wherein forming the gate electrode further comprises:

filling a fill material in the first trench so that the fill material protrudes from the top surface of the semiconductor substrate, the protruding fill material having sidewalls; and

forming a spacer of a sacrificial material adjacent to the sidewalls.

20. The method according to claim 19, wherein the fill material is a conductive material.

21. The method according to claim 19, further comprising etching the second trenches in the top surface of the semiconductor substrate, using the protruding fill material and the spacer as an etching mask.