SEMICONDUCTOR DEVICE

• US 20140084434A1
• Filed: 09/03/2013
• Published: 03/27/2014
• Est. Priority Date: 09/24/2012
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KANEMOTO, Koichi, IMURA, Chikako
• Granted Patent: US 8,987,882 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.

Claims

1. A semiconductor device, comprising:

a die pad having an upper surface and a lower surface opposite to the upper surface, a shape in a plan view of the upper surface comprised of quadrangle;

a plurality of suspension leads supporting corner parts of the die pad, respectively;

a plurality of lead groups arranged along sides of the die pad, respectively, in the plan view;

a first semiconductor chip having a first main surface, a plurality of first pad groups formed along sides of the first main surface, respectively, and a first back surface opposite to the first main surface, and arranged over the upper surface of the die pad, and arranged at the central part of the die pad in the plan view such that the first back surface faces to the upper surface of the die pad, and such that the sides of the first main surface are arranged in parallel with the sides of the upper surface of the die pad, respectively, in the plan view;

a second semiconductor chip having a second main surface, a second pad group formed over the second main surface, and a second back surface opposite to the second main surface, and arranged over the upper surface of the die pad, and arranged next to the first semiconductor chip in the plan view; and

a plurality of first down bonding wire groups electrically connecting the first pad groups of the first semiconductor chip with a plurality of down bonding regions of the die pad, respectively,

wherein a length of a side of the second main surface of the second semiconductor chip is larger than the distance between a first down bonding region of the down bonding regions of the die pad and a first die pad side of the sides of the upper surface of the die pad, the first die pad side being closest to the first down bonding region, and

wherein the second semiconductor chip is arranged in a corner part region between the first down bonding region formed along the first die pad side of the die pad and a second down bonding region formed along a second die pad side crossing with the first die pad side in the plan view.

2. The semiconductor device according to claim 1,

wherein a part of the second semiconductor chip is arranged between the first semiconductor chip and the side of the upper surface of the die pad in a plan view.

3. The semiconductor device according to claim 2,

wherein the first semiconductor chip is mounted over the upper surface of the die pad such that a first region surrounded by a plurality of first pads formed along each side of the first main surface of the first semiconductor chip overlaps a point of intersection between respective extension lines of the suspension leads in a plan view.

4. The semiconductor device according to claim 3,

wherein the second semiconductor chip is mounted over the upper surface of the die pad such that a second region surrounded by a plurality of second pads formed along a plurality of sides of the second main surface of the second semiconductor chip overlaps a part of either of two diagonal lines of the upper surface of the die pad in a plan view.

5. The semiconductor device according to claim 3,

wherein the first semiconductor chip is stacked over a third semiconductor chip mounted over the upper surface of the die pad, and

wherein the third semiconductor chip juts out from the first semiconductor chip toward the side of the die pad opposite to the side thereof over which the second semiconductor chip is mounted.

6. The semiconductor device according to claim 3,

wherein in the die pad, a step part with the upper surface protruding from the lower surface is formed.

7. The semiconductor device according to claim 6,

wherein the step part is formed with the protrusion amount being larger on the side of the die pad over which the second semiconductor chip is mounted than on the opposite side therefrom.

8. The semiconductor device according to claim 7,

wherein a sealing body for sealing the first, second, and third semiconductor chips is formed, and the lower surface of the die pad is exposed at the back surface of the sealing body.