MICRO DEVICE STABILIZATION POST

• US 20140084482A1
• Filed: 12/11/2012
• Published: 03/27/2014
• Est. Priority Date: 09/24/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Hu, Hsin-Hua, Bibl, Andreas, Higginson, John A.
• Granted Patent: US 8,941,215 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 2224/83409 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/83411 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/83444 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/83815 Reflow soldering
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Claims

1. A structure comprising:

a stabilization layer comprising an array of stabilization posts;

an array of micro chips on the array of stabilization posts;

wherein each micro chip includes bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

2. The structure of claim 1, further comprising an array of bottom conductive contacts on the bottom surfaces of the array of micro chips.

3. The structure of claim 2, wherein each micro chip comprises a contact pad in electrical connection with one of the conductive contacts.

4. The structure of claim 1, wherein the stabilization layer is formed of a thermoset material.

5. The structure of claim 4, wherein the thermoset material comprises benzocyclobutene (BCB).

6. The structure of claim 1, wherein the array of stabilization posts are separated by a pitch of 1 μ

m to 100 μ

m.

7. The structure of claim 1, wherein the array of stabilization posts are separated by a pitch of 1 μ

m to 10 μ

m.

8. The structure of claim 1, wherein the stabilization layer is bonded to a carrier substrate.

9. The structure of claim 1, further comprising a sacrificial layer between the stabilization layer and the array of micro chips, wherein the array of stabilization posts extend through a thickness of the sacrificial layer.

10. The structure of claim 9, wherein the sacrificial layer comprises an oxide or nitride.

11. The structure of claim 9, further comprising an etch stop detection layer between the sacrificial layer and the array of micro chips, wherein the array of stabilization posts extend through a thickness of the etch stop detection layer.

12. The structure of claim 11, wherein the etch stop detection layer comprises titanium.

13. The structure of claim 9, further comprising an adhesion promoter layer between the stabilization layer and the sacrificial layer, wherein the array of stabilization posts extend through a thickness of the adhesion promoter layer.

14. The structure of claim 1, wherein each micro chip has a maximum width of 1 to 100 μ

m.

15. The structure of claim 14, wherein each micro chip is on a plurality of stabilization posts.

16. The structure of claim 15, wherein each micro chip comprises a through via extending completely though the micro chip, wherein the through via is not directly above a stabilization post.

17-25. -25. (canceled)