LOW DROPOUT REGULATOR WITH HYSTERETIC CONTROL

• US 20140084881A1
• Filed: 09/25/2012
• Published: 03/27/2014
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jain, Rinkle, Shih, Yi-Chun, Vaidya, Vaibhav
• Granted Patent: US 9,323,263 B2
• Time in Patent Office: Days
• US Class Current: 323/269
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence

Abstract

Described is an apparatus comprising: an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load; an amplifier to control current strength of the output stage according to the output supply and a reference voltage; and a hysteresis unit to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply. Described is another apparatus which comprises: a plurality of charge pumps to adjust current strength of the output stage; and a logic unit to monitor the output supply and operable to control the plurality of charge pumps according to a voltage level of the output supply and one or more reference voltages.

Claims

1. An apparatus comprising:

an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load;

an amplifier to control current strength of the output stage according to the output supply and a reference voltage; and

a circuit to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply.

2. The apparatus of claim 1, wherein the output stage comprises:

a first stage coupled to the amplifier; and

a second stage operable to be selectively turned on or off by the circuit.

3. The apparatus of claim 2, wherein the first and second stages are normally on.

4. The apparatus of claim 2, wherein the second stage is operable to be turned off when the output supply overshoots.

5. The apparatus of claim 2, wherein the output stage comprises:

a third stage operable to be selectively turned on or off by the circuit.

6. The apparatus of claim 5, wherein the third stage is normally off.

7. The apparatus of claim 6, wherein the third stage is operable to be turned on when the output supply undershoots.

8. The apparatus of claim 5, wherein the first, second, and third stages comprise first, second, and third p-type transistors respectively coupled between the input supply node and the output node.

9. The apparatus of claim 2, wherein the circuit comprises:

a first comparator to compare the output supply relative to a first reference, the first comparator to generate a first output to control current strength of the second stage, wherein the first reference is different from the reference voltage.

10. The apparatus of claim 5, wherein the circuit comprises:

a second comparator to compare the output supply relative to a second reference, the second comparator to generate a second output to control current strength of the third stage, wherein the second reference is different from the reference voltage.

11. The apparatus of claim 5 further comprises:

a bias circuit coupled to the third stage, the bias circuit to adjust current strength of the third stage.

12. The apparatus of claim 11, wherein the bias circuit to generate a charging current for adjusting current strength of the third stage, wherein the bias circuit is operable to adjust the charging current according to the reference voltage.

13. The apparatus of claim 11, wherein the bias circuit comprises a replica regulator.

14. The apparatus of claim 1 further comprises:

a charge pump coupled to an output of the amplifier, the charge pump operable to adjust a voltage level of the output of the amplifier.

15. The apparatus of claim 14, wherein the charge pump to add charge to the output of the amplifier when the output supply overshoots.

16. The apparatus of claim 14, wherein the charge pump to subtract charge from the output of the amplifier when the output supply undershoots.

17. A system comprising:

a memory;

a processor, coupled to the memory, the processor including a low dropout regulator comprising;

an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load;

an amplifier to control current strength of the output stage according to the output supply and a reference voltage; and

a circuit to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply; and

a wireless interface to communicatively couple the processor with another device.

18. The system of claim 17 further comprises a display unit.

19. An apparatus comprising:

an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load;

a plurality of charge pumps to adjust current strength of the output stage; and

a logic unit to monitor the output supply and operable to control the plurality of charge pumps according to a voltage level of the output supply and one or more reference voltages.

20. The apparatus of claim 19, wherein the logic unit comprises:

a first comparator to cause a first charge pump, from the plurality of charge pumps, to reduce drive strength of the output stage when the output supply is greater than a first reference voltage.

21. The apparatus of claim 20, wherein the logic unit comprises:

a second comparator to cause a second charge pump, from the plurality of charge pumps, to increase drive strength of the output stage when the output supply is less than a second reference voltage.

22. The apparatus of claim 21, wherein the logic unit comprises:

a third comparator to cause a third charge pump, from the plurality of charge pumps, to reduce drive strength of the output stage when the output supply is greater than a third reference voltage.

23. The apparatus of claim 22, wherein the logic unit comprises:

a fourth comparator to cause a fourth charge pump, from the plurality of charge pumps, to increase drive strength of the output stage when the output supply is less than a fourth reference voltage.

24. The apparatus of claim 23 further comprises:

a reference generator to generate the first, second, third, and fourth reference voltages.

25. The apparatus of claim 23, wherein fourth reference is higher than the first, second, and third voltage references.

26. The apparatus of claim 23, wherein the third reference is lower than the first, second, and fourth voltage references.

27. The apparatus of claim 23, wherein the first reference is higher than the second and third voltage references.

28. The apparatus of claim 19, wherein the output stage comprises a p-type transistor with a gate terminal coupled directly or indirectly to the plurality of charge pumps, a source terminal coupled directly or indirectly to the input supply node, and a drain terminal coupled directly or indirectly to the output node.

29. The apparatus of claim 19, wherein one or more charge pumps from the plurality of charge pumps are operable to have different charging strengths.