Delay-Locked Loop with Dynamically Biased Charge Pump

• US 20140084976A1
• Filed: 11/21/2013
• Published: 03/27/2014
• Est. Priority Date: 02/04/2005
• Status: Active Grant

• Current Assignee: True Circuits, Inc.
• Original Assignee: True Circuits, Inc.
• Inventors: Maneatis, John George, Kim, Jaeha, Hartman, Daniel Karl
• Granted Patent: US 8,867,685 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses

Abstract

A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Claims

1. A delay-locked loop, comprising:

a first delay line;

a second delay line;

a first phase detector coupled to outputs of the first and second delay lines, the first phase detector including an UP output and a DOWN output;

a second phase detector coupled to inverted outputs of the first and second delay lines, the second phase detector including an UP output and a DOWN output;

a first charge pump coupled to the first phase detector so that the UP output of the first phase detector is coupled to a first charge pump input of the first charge pump and so that the DOWN output of the first phase detector is coupled to a second charge pump input of the first charge pump, where the first charge pump is configured to pump charge via a charge pump output of the first charge pump based on a bias condition and on levels at the first charge pump input of the first charge pump and the second charge pump input of the first charge pump; and

a second charge pump coupled to the second phase detector so that the UP output of the second phase detector is coupled to a first charge pump input of the second charge pump and so that the DOWN output of the second phase detector is coupled to a second charge pump input of the second charge pump, where the second charge pump is configured to pump charge via a charge pump output of the second charge pump based on a bias condition and on levels at the first charge pump input of the second charge pump and the second charge pump input of the second charge pump.

2. The delay-locked loop of claim 1, where the first and second phase detectors are coupled to the first and second delay lines, with the delay-locked loop being configured to lock relative delay between the first and second delay lines to one reference cycle.

3. The delay-locked loop of claim 1, further comprising one or more slave delay lines using the same biasing as the first and second delay lines.

4. The delay-locked loop of claim 3, where the number of selected stages in the one or more slave delay lines delays a signal substantially by a precise fraction of the clock period beyond the delay which would result from the minimum number of selected stages.

5. A delay-locked loop, comprising:

a delay line;

a phase detector coupled to an output of the delay line, the phase detector including an UP output and a DOWN output;

a charge pump coupled to the phase detector so that the UP output of the phase detector is coupled to a first charge pump input of the charge pump and so that the DOWN output of the phase detector is coupled to a second charge pump input of the charge pump, where the charge pump is configured to pump charge via a charge pump output based on a bias condition and on levels at the first charge pump input and the second charge pump input;

a charge pump replica coupled with the charge pump and configured to dynamically adjust the bias condition so that, in response to an assertion condition at the first charge pump input and the second charge pump input, the charge pump pumps a net charge that tends toward a desired value associated with such assertion condition; and

a delay regulator coupled to the delay line and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of the delay line.

6. The delay-locked loop of claim 5, where the assertion condition is a simultaneous assertion of activating signals at the first charge pump input and the second charge pump input.

7. The delay-locked loop of claim 6, where the desired value is substantially zero net charge.

8. The delay-locked loop of claim 5, where the charge pump and the charge pump replica each have a first common bias input and a second common bias input.

9. The delay-locked loop of claim 8, where the charge pump output and a charge pump replica output are coupled to a differential amplifier, and where an output of the differential amplifier biases at least one of the first common bias input and the second common bias input.

10. The delay-locked loop of claim 8, where the charge pump output and a charge pump replica output are operatively coupled to the first common bias input and the second common bias input.

11. The delay-locked loop of claim 5, further comprising a second delay line, where the phase detector is coupled to an output of the second delay line.

12. A delay-locked loop, comprising:

a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output; and

a charge pump system operatively coupled with the phase detector and including;

a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals;

a delay regulator coupled to the delay line and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of the delay line; and

a current compensation circuit coupled to the delay regulator and configured to operate in one of an activated state, in which the current compensation circuit draws current from the delay regulator, and a deactivated state, in which the current compensation circuit draws substantially no current from the delay regulator.

13. The delay-locked loop of claim 12, where the current compensation circuit is configured to operate in the activated state when substantially no current is being drawn from the delay regulator by the delay line.

14. The delay-locked loop of claim 13, where the current compensation circuit is configured so that, in the activated state, it draws current substantially equivalent to that drawn by the delay line when a signal edge is propagating through the delay line.

15. The delay-locked loop of claim 12, where the current compensation circuit is configured to operate in the deactivated state when a signal edge is propagating through the delay line.

16. A delay-locked loop, comprising:

a delay line composed of delay elements using only NAND gates in a signal delay path of the delay line;

a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output; and

a charge pump system operatively coupled with the phase detector and including;

a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control the delay line so as to control relative delay occurring between the two signals; and

a delay regulator coupled to the delay line and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of the delay line.

17. The delay-locked loop of claim 16, where NAND gates are used to multiplex the signal delay path in order to control (i) a number of selected stages in the delay line, or (ii) a length of the delay line.

18. The delay-locked loop of claim 16, where the NAND gates in the signal delay path are flip-stack NAND gates.