SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

• US 20140085122A1
• Filed: 02/08/2013
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: JEON, Young-deuk, ROH, Tae Moon, KWON, Jong-Kee
• Granted Patent: US 8,717,221 B2
• Time in Patent Office: Days
• US Class Current: 341/158
• CPC Class Codes: H03M 1/0678 using additional components or elements, e.g. dummy components
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

Claims

1. A successive approximation register analog-to-digital converter comprising:

first and second capacitor arrays configured to generate first and second level voltages, respectively;

a comparator configured to compare the first and second level voltages to output a comparison signal;

SAR logic configured to generate a digital signal in response to the comparison signal; and

a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to the comparison result.

2. The successive approximation register analog-to-digital converter of claim 1, wherein the first capacitor array samples the first analog input voltage and the second capacitor array samples a second analog input voltage, the first analog input voltage being included in a power supply voltage range and the second analog input voltage being half a power supply voltage.

3. The successive approximation register analog-to-digital converter of claim 2, wherein the variable common mode selector comprises:

a comparator configured to compare the first analog input voltage and the common mode voltage; and

switches configured to select one of the first analog input voltage and the common mode voltage according to an output of the comparator.

4. The successive approximation register analog-to-digital converter of claim 3, wherein the variable common mode selector provides the top plates of the first and second capacitor arrays with the first analog input voltage when the first analog input voltage is higher than the common mode voltage and with the common mode voltage when the first analog input voltage is lower than the common mode voltage.

5. The successive approximation register analog-to-digital converter of claim 1, further comprising:

a clock generator configured to generate a sampling clock and a conversion clock, and

wherein the first and second capacitor arrays sample the first and a second analog input voltage in response to the sampling clock and output the first and second level voltages in response to the conversion clock.

6. The successive approximation register analog-to-digital converter of claim 5, wherein the SAR logic responds to the conversion clock to decide a digital signal based on an output of the comparator.

7. The successive approximation register analog-to-digital converter of claim 5, wherein the variable common mode selector selects one of the first analog input voltage and the common mode voltage in response to the sampling clock to be supplied to the top plates of the first and second capacitor arrays.

8. The successive approximation register analog-to-digital converter of claim 1, wherein one of first and second reference voltages is supplied to bottom plates of the first and second capacitor arrays based on the digital signal.

9. The successive approximation register analog-to-digital converter of claim 1, wherein the common mode voltage is half a power supply voltage.