METHOD AND ARCHITECTURE FOR IMPROVING DEFECT DETECTABILITY, COUPLING AREA, AND FLEXIBILITY OF NVSRAM CELLS AND ARRAYS
First Claim
1. A Nonvolatile SRAM (NVSRAM) cell with marginal threshold level detection, the NVSRAM cell comprising:
- a SRAM cell comprising a first inverter having a first output node and a second inverter having a second output node, the first output node and the second output node being coupled to a first word line and two bit lines respectively via a first access transistor and a second access transistor, the first inverter and the second inverter being respectively associated with a first current and a second current sharing a common power line configured to add an adjustable resistor;
a first Flash cell comprising a first string having at least a first flash transistor sandwiched by a first select transistor and a second select transistor connected in series from a first drain terminal to a first source terminal, and comprising a second string having a second flash transistor sandwiched by a third select transistor and a fourth select transistor connected in series from a second drain terminal to a second source terminal, the first select transistor and the third select transistor being commonly gated by a first select control signal, the second select transistor and the fourth select transistor being commonly gated by a second select control signal, the first flash transistor and the second flash transistor having their gates commonly coupled to a second word line signal to control a third current through the first string from the first drain terminal to the first source terminal and a fourth current through the second string from the second drain terminal to the second source terminal, the first source terminal and the second source terminal being respectively coupled to a first source line and a second source line;
wherein the first drain terminal and the second drain terminal of the first Flash cell are coupled to either the first output node or the second output node of the SRAM cell to form a differential amplifier having one paired driver device made by the first string and the second string of the first Flash cell and one paired load device made by the first inverter and the second inverter of the SRAM cell, the second word line being configured to provide one paired input of the differential amplifier for yielding one paired output respectively to the first output node and the second output node, the adjustable resistor being configured to be substantially larger than an effective resistance of either the first string or the second string for providing a greater than 3;
1 ratio between a largest one of the third current and the fourth current over a largest one of the first current and the second current when writing a first logic state associated with a combination of two threshold levels of the first flash transistor and the second flash transistor into a second logic state associated with a combination of either a VSS=0V or a low-voltage VDD level at the first output node and the second output node.
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Accused Products
Abstract
Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect the marginally erased Vt0 and marginally programmed Vt1 of the paired flash cell. By increasing an resistance added to common SRAM power line, the pull-down current through flash Strings to grounding source line can be made much larger than the pull-up current to improve SFwrite program operation. Simple method by increasing flash cell channel length to effectively enhance coupling area is applied to secure SRAM-to-Flash store operation under self-boost-program-inhibit scheme. 1S2F architecture also provide flexibility for alternate erasing and programming during both a recall and store operation.
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Citations
47 Claims
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1. A Nonvolatile SRAM (NVSRAM) cell with marginal threshold level detection, the NVSRAM cell comprising:
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a SRAM cell comprising a first inverter having a first output node and a second inverter having a second output node, the first output node and the second output node being coupled to a first word line and two bit lines respectively via a first access transistor and a second access transistor, the first inverter and the second inverter being respectively associated with a first current and a second current sharing a common power line configured to add an adjustable resistor; a first Flash cell comprising a first string having at least a first flash transistor sandwiched by a first select transistor and a second select transistor connected in series from a first drain terminal to a first source terminal, and comprising a second string having a second flash transistor sandwiched by a third select transistor and a fourth select transistor connected in series from a second drain terminal to a second source terminal, the first select transistor and the third select transistor being commonly gated by a first select control signal, the second select transistor and the fourth select transistor being commonly gated by a second select control signal, the first flash transistor and the second flash transistor having their gates commonly coupled to a second word line signal to control a third current through the first string from the first drain terminal to the first source terminal and a fourth current through the second string from the second drain terminal to the second source terminal, the first source terminal and the second source terminal being respectively coupled to a first source line and a second source line; wherein the first drain terminal and the second drain terminal of the first Flash cell are coupled to either the first output node or the second output node of the SRAM cell to form a differential amplifier having one paired driver device made by the first string and the second string of the first Flash cell and one paired load device made by the first inverter and the second inverter of the SRAM cell, the second word line being configured to provide one paired input of the differential amplifier for yielding one paired output respectively to the first output node and the second output node, the adjustable resistor being configured to be substantially larger than an effective resistance of either the first string or the second string for providing a greater than 3;
1 ratio between a largest one of the third current and the fourth current over a largest one of the first current and the second current when writing a first logic state associated with a combination of two threshold levels of the first flash transistor and the second flash transistor into a second logic state associated with a combination of either a VSS=0V or a low-voltage VDD level at the first output node and the second output node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A 14-transistor NVSRAM cell for flexible recall and store operations, the 14T NVSRAM cell comprising:
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a SRAM cell comprising a first inverter associated with a first data node and a second inverter associated with a second data node, the first data node and the second data node being coupled to a first word line and two complementary bit lines respectively via a first access transistor and a second access transistor; a Flash cell comprising a first string from a first drain terminal to a first source terminal and a second string from a second drain terminal to a second source terminal, the first string having a first select transistor, a first flash transistor, a second flash transistor, and a second select transistor connected in series, the second string having a third select transistor, a third flash transistor, a fourth flash transistor, and a fourth select transistor connected in series, the first flash transistor and the third flash transistor being commonly gated by a second word line signal, the second flash transistor and the fourth flash transistor being commonly gated by a third word line, the first select transistor and the third select transistor being commonly gated by a first select control signal, the second select transistor and the fourth select transistor being commonly gated by a second select control signal, the first source terminal and the second source terminal being respectively coupled to a first source line and a second source line; wherein the first drain terminal and the second drain terminal of the Flash cell are respectively coupled to the first data node or the second data node of the SRAM cell, a first pair of the first flash transistor and the third flash transistor and a second pair of the second flash transistor and the fourth flash transistor are alternatively erased and programmed for storing either an old logic data or an updated logic data associated with a combination of two voltage levels at the first data node and the second data node of the SRAM cell during both a Store operation and a Recall operation. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A NVSRAM chip capable of flexibly detecting defect bits in the unit of bit, page, and chip, the NVSRAM chip comprising,
an NVSRAM memory array formed by M× - N NVSRAM cells in a matrix of M rows and N columns, each NVSRAM cell comprising a SRAM cell coupled to a Flash cell having two flash strings corresponding to a pair of flash transistors, each row forming a page commonly associated with a SRAM word line and a VSS ground line, a SRAM Vdd power line, a pair of select gate controls, a Flash word line, and a Flash source line dividable to connect respectively to the two flash strings in each Flash cell in each NVSRAM cell, each column being coupled with a pair bit lines coupled respectively to a first output node and a second output node of each SRAM cell in each NVSRAM cell;
a SRAM X-decoder coupled with the NVSRAM memory array from X-direction to provide per each row a decoding signal to the SRAM word line and a grounding line; a Flash X-decoder coupled with the NVSRAM memory array from X-direction to provide per each row a variable signal for the Flash word line, control signals for the pair of select gate controls, and one or two bias levels to the dividable Flash source line, and to provide an on-chip VDD power supply configured to couple with each SRAM Vdd power line via a PN-paired device as an adjustable resistor; a Match decoder coupled to the Flash X-decoder for further providing a match signal per each row sent through the Flash source line to each NVSRAM cell; a Y-decoder configured to provides per column a pair of decoding bits for the pair of bit lines; a SRAM sense amplifier; an I/O buffer device; a CE buffer device; an OE buffer device; and an Address buffer; wherein the NVSRAM memory array is subjected to a flash status verification operation configured for flexibly detecting and defect bits of one or more flash transistors and screening out low marginal threshold level cells in the whole NVSRAM memory array. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
- N NVSRAM cells in a matrix of M rows and N columns, each NVSRAM cell comprising a SRAM cell coupled to a Flash cell having two flash strings corresponding to a pair of flash transistors, each row forming a page commonly associated with a SRAM word line and a VSS ground line, a SRAM Vdd power line, a pair of select gate controls, a Flash word line, and a Flash source line dividable to connect respectively to the two flash strings in each Flash cell in each NVSRAM cell, each column being coupled with a pair bit lines coupled respectively to a first output node and a second output node of each SRAM cell in each NVSRAM cell;
Specification