COMMUNICATION OF DEVICE PRESENCE BETWEEN BOOT ROUTINE AND OPERATING SYSTEM

• US 20140089551A1
• Filed: 09/26/2012
• Published: 03/27/2014
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Estrada, David C., Zimmer, Vincent J., Sakthikumar, Palsamy
• Granted Patent: US 9,292,463 B2
• Time in Patent Office: Days
• US Class Current: 710/312
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.

Claims

1. An apparatus comprising:

a first processor circuit; and

a first storage communicatively coupled to the first processor circuit and arranged to store a first sequence of instructions operative on the first processor circuit to;

create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the first processor circuit, the device blocks arranged in an order within the device table indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device of the multiple hardware devices;

enable access to the device table by an operating system; and

execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table.

2. The apparatus of claim 1, the first sequence of instructions operative on the first processor circuit to:

detect multiple bridge devices among the multiple hardware devices; and

arrange device blocks of the multiple device blocks corresponding to bridge devices of the multiple bridge devices in the device table in order of decreasing closeness of coupling of each corresponding bridge device to the first processor circuit.

3. The apparatus of claim 1, the first sequence of instructions operative on the first processor circuit to arrange the device blocks of the multiple device blocks within the device table such that a device block corresponding to a core device of the multiple hardware devices precedes all other device blocks.

4. The apparatus of claim 1, the first sequence of instructions operative on the first processor circuit to:

detect the at least one bridge device;

detect at least one endpoint device among the multiple hardware devices; and

arrange device blocks of the multiple device blocks corresponding to the at least one bridge device and the at least one endpoint device within the device table such that all device blocks corresponding to the at least one bridge device precede all device blocks corresponding to the at least one endpoint device.

5. The apparatus of claim 4, the at least one endpoint device comprising one of controls, a storage device, an interface controller operative to communicatively couple the first processor circuit to a network, and a display interface.

6. The apparatus of claim 1, comprising:

a second processor circuit; and

a second storage communicatively coupled to the second processor circuit and arranged to store a third sequence of instructions operative on the second processor circuit to;

access the first storage;

read the first sequence of instructions; and

authenticate the first sequence of instructions.

7. The apparatus of claim 1, the first sequence of instructions operative on the first processor circuit to load multiple device drivers, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks, in an order corresponding to the order in which the device blocks are arranged within the device table.

8. The apparatus of claim 7, each device block of the multiple device blocks comprising data and/or executable code;

and each device block specifying an aspect of interaction between a device driver of the multiple device drivers and a hardware device of the multiple hardware devices, the aspect of interaction comprising at least one of parameters passed, a result code returned, an available initialization routine, an available reset routine, a power state control routine, a type of I/O access, a type of memory access, a mechanism to determine a physical address, a mechanism to determine a virtual address, and an error condition.

9. The apparatus of claim 1, the second sequence of instructions operative on the first processor circuit to load multiple device drivers, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks, in an order corresponding to the order in which the device blocks are arranged within the device table.

10. An apparatus comprising:

a first processor circuit; and

a first storage communicatively coupled to the first processor circuit and arranged to store a first sequence of instructions operative on the first processor circuit to;

enable access by an operating system to a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the first processor circuit, the device blocks arranged in an order within the device table indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device of the multiple hardware devices; and

execute the second sequence of instructions, the second sequence of instructions operable to access the device table.

11. The apparatus of claim 10, comprising:

a second processor circuit; and

a second storage communicatively coupled to the second processor circuit and arranged to store a third sequence of instructions operative on the second processor circuit to;

access the first storage;

read the first sequence of instructions; and

authenticate the first sequence of instructions.

12. The apparatus of claim 10, comprising:

a second processor circuit; and

a second storage communicatively coupled to the second processor circuit and arranged to store the device table and a third sequence of instructions operative on the second processor circuit to copy the device table from the second storage to the first storage.

13. The apparatus of claim 10, comprising:

a second processor circuit; and

a second storage communicatively coupled to the second processor circuit and arranged to store a hash of the device table and a third sequence of instructions operative on the second processor circuit to await a signal requesting authentication of the device table with the hash of the device table, the second sequence of instructions operative on the first processor circuit to provide the signal to the second processor circuit.

14. The apparatus of claim 10, the first sequence of instructions operative on the first processor circuit to load multiple device drivers, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks, in an order corresponding to the order in which the device blocks are arranged within the device table.

15. The apparatus of claim 10, the second sequence of instructions operative on the first processor circuit to load multiple device drivers, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks, in an order corresponding to the order in which the device blocks are arranged within the device table.

16. The apparatus of claim 15, each device block of the multiple device blocks comprising data and/or executable code;

and each device block specifying an aspect of interaction between a device driver of the multiple device drivers and a hardware device of the multiple hardware devices, the aspect of interaction comprising at least one of parameters passed, a result code returned, an available initialization routine, an available reset routine, a power state control routine, a type of I/O access, a type of memory access, a mechanism to determine a physical address, a mechanism to determine a virtual address, and an error condition.

17. A computer-implemented method comprising:

creating a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices of a computing device accessible to a first processor circuit of the computing device, the device blocks arranged in an order within the device table indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device of the multiple hardware devices;

enabling access to the device table by an operating system;

loading the operating system; and

accessing the device table following loading the operating system.

18. The computer-implemented method of claim 17, comprising authenticating a boot routine stored in a first storage of the computing device accessible to the first processor circuit, the boot routine comprising a sequence of instructions operative on the first processor circuit to create the device table.

19. The computer-implemented method of claim 17, comprising:

detecting multiple bridge devices among the multiple hardware devices; and

arranging device blocks of the multiple device blocks corresponding to bridge devices of the multiple bridge devices in the device table in order of decreasing closeness of coupling of each corresponding bridge device to the first processor circuit.

20. The computer-implemented method of claim 17, comprising arranging the device blocks of the multiple device blocks within the device table such that a device block corresponding to a core device of the multiple hardware devices precedes all other device blocks.

21. The computer-implemented method of claim 17, comprising:

detecting the at least one bridge device;

detecting at least one endpoint device among the multiple hardware devices; and

arranging device blocks of the multiple device blocks corresponding to the at least one bridge device and the at least one endpoint device within the device table such that all device blocks corresponding to the at least one bridge device precede all device blocks corresponding to the at least one endpoint device.

22. The computer-implemented method of claim 21, the at least one endpoint device comprising one of controls, a storage device, an interface controller operative to communicatively couple the computing device to a network, and a display interface.

23. The computer-implemented method of claim 17, comprising loading multiple device drivers, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks, in an order corresponding to the order in which the device blocks are arranged within the device table.

24. The computer-implemented method of claim 17, comprising signaling a second processor circuit to request authentication of the device table using a hash of the device table stored in a storage communicatively coupled to the second processor circuit following loading the operating system.

25. At least one machine-readable storage medium comprising a first sequence of instructions that when executed by a computing device, causes the computing device to:

create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices of the computing device accessible to the first processor circuit of the computing device, the device blocks arranged in an order within the device table indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device of the multiple hardware devices;

enable access to the device table by an operating system; and

execute a second sequence of instructions of the operating system that cause the computing device to access the device table.

26. The at least one machine-readable storage medium of claim 25, the computing device caused to:

detect multiple bridge devices among the multiple hardware devices; and

arrange device blocks of the multiple device blocks corresponding to bridge devices of the multiple bridge devices in the device table in order of decreasing closeness of coupling of each corresponding bridge device to the first processor circuit.

27. The at least one machine-readable storage medium of claim 25, the computing device caused to arrange the device blocks of the multiple device blocks within the device table such that a device block corresponding to a core device of the multiple hardware devices precedes all other device blocks.

28. The at least one machine-readable storage medium of claim 25, the computing device caused to:

detect the at least one bridge device;

detect at least one endpoint device among the multiple hardware devices; and

arrange device blocks of the multiple device blocks corresponding to the at least one bridge device and the at least one endpoint device within the device table such that all device blocks corresponding to the at least one bridge device precede all device blocks corresponding to the at least one endpoint device.

29. The at least one machine-readable storage medium of claim 28, the at least one endpoint device comprising one of controls, a storage device, an interface controller operative to communicatively couple the computing device to a network, and a display interface.

30. The at least one machine-readable storage medium of claim 25, the computing device caused to load multiple device drivers, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks, in an order corresponding to the order in which the device blocks are arranged within the device table.