Sharing Power Between Domains In A Processor Package

• US 20140089688A1
• Filed: 09/27/2012
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Man, Xiuting C., Ananthakrishnan, Avinash N., Derr, Michael N., Forbell, Craig
• Granted Patent: US 9,423,858 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a first domain including at least one core to execute instructions;

a second domain coupled to the first domain and including at least one non-core circuit, wherein the first and second domains are configured to operate at independent frequencies; and

a power control unit (PCU) coupled to the first and second domains, the PCU including a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information.

2. The processor of claim 1, wherein the PCU further comprises a power calculation logic to calculate a package power consumption value based on the encoded power consumption information and a first domain power consumption value, and to communicate the package power consumption value to at least one agent external to the processor.

3. The processor of claim 2, wherein the at least one agent comprises an embedded controller, the embedded controller to adjust a speed of a fan responsive to the communication of the package power consumption value.

4. The processor of claim 1, wherein the first domain further comprises a non-volatile storage to store a plurality of power consumption values for a peripheral controller of the second domain, each of the power consumption values corresponding to a consumption level for a test scenario executed on the peripheral controller during high volume manufacturing testing.

5. The processor of claim 4, wherein the second domain further comprises a plurality of threshold registers each to store one of the plurality of power consumption values, wherein the plurality of power consumption values are to be communicated to the plurality of threshold registers from the non-volatile storage of the first domain via a basic input/output system (BIOS) during initialization of the processor.

6. The processor of claim 5, wherein the second domain further comprises a power meter, the power meter to estimate a power consumption value of the peripheral controller during normal operation.

7. The processor of claim 6, further comprising a detection logic to determine which of the plurality of threshold registers has a power consumption value correlating to the power consumption value estimate, and to communicate the encoded power consumption information corresponding to the correlating power consumption value.

8. The processor of claim 7, wherein the PCU comprises a monitor logic to receive the encoded power control information and to access a lookup table to determine the correlating power consumption value.

9. The processor of claim 8, wherein the PCU comprises a power budget update logic to calculate the available power budget for the first domain based on a total power budget for the processor and the correlating power consumption value.

10. A processor comprising:

at least one core to execute instructions and corresponding to a first domain;

a peripheral controller coupled to the at least one core and corresponding to a second domain, the peripheral controller to interface the at least one core to at least one peripheral device, the peripheral controller including a power meter to estimate a power consumption level of the peripheral controller and a detector to communicate a value of the power consumption level, the first and second domains to share a common power budget; and

a power controller coupled to the at least one core and the peripheral controller, wherein the power controller includes a power budget update logic to determine an updated power budget for the first domain responsive to the power consumption level value and to cause a frequency of the at least one core to be updated based at least in part on the updated power budget.

11. The processor of claim 10, wherein the at least one core and the peripheral controller are configured within a processor package.

12. The processor of claim 10, further comprising an interface coupled between the first domain and the second domain to communicate the power consumption level value comprising encoded power consumption information, the interface comprising a serial interface coupled between a first die including the first domain and a second die including the second domain.

13. The processor of claim 12, wherein the encoded power consumption information comprises an index value of a threshold register of the peripheral controller having a power consumption value correlating to the power consumption level estimate.

14. The processor of claim 13, wherein the power controller comprises a monitor logic to receive the encoded power consumption information and to access a lookup table to determine the correlating power consumption value.

15. The processor of claim 14, wherein the power controller comprises a power budget update logic to calculate the updated power budget for the first domain based on a total power budget for the processor and the correlating power consumption value.

16. A system comprising:

a multi-domain processor including a first die having a core domain including a plurality of cores, a graphics domain including at least one graphics engine, and a system agent domain including a power controller, and a second die having a peripheral controller and coupled to the first die via a communication path to communicate an index value corresponding to an estimate of power consumption by the peripheral controller, wherein the power controller is to calculate an available power budget for the first die and to control a frequency of at least one of the core domain and the graphics domain based at least in part on the available budget; and

a dynamic random access memory (DRAM) coupled to the multi-domain processor.

17. The system of claim 16, wherein the first die includes a non-volatile storage to store a plurality of power consumption values each corresponding to a consumption level for a test scenario executed on the peripheral controller during high volume manufacturing testing.

18. The system of claim 17, wherein the peripheral controller includes:

a power meter to estimate a power consumption value of the peripheral controller during normal operation; and

a detection logic to determine which of a plurality of threshold registers has a power consumption value correlating to the power consumption value estimate, wherein the detection logic is to communicate the index value corresponding to the correlating power consumption value.

19. The system of claim 17, wherein the multi-domain processor is to write the plurality of power consumption values from the non-volatile storage of the first die to a plurality of threshold registers of the second die, each to store one of the plurality of power consumption values during initialization of the processor.

20. The system of claim 16, further comprising a power budget update logic to calculate the available power budget for the first die based on a total power budget for the multi-domain processor and the index value, wherein the available power budget includes a first updated power budget for a steady state budget and a second updated power budget for an instantaneous state budget.