SYSTEM-ON-CHIP WITH CAPABILITY FOR CONTROLLING POWER SUPPLY ACCORDING TO DATA TRANSACTION AND METHOD OF OPERATING THE SAME

• US 20140089697A1
• Filed: 09/04/2013
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Ju Hwan Kim, Jun-ho Heo, Kee Moon Chun, Soo Yong Kim
• Inventors: KIM, SOO YONG, KIM, JU HWAN, HUH, JUN HO, CHUN, KEE MOON
• Granted Patent: US 9,395,777 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A system-on-chip (SoC) which includes a plurality of intellectual properties (IP cores) which communicate data with a memory device operates by monitoring whether a data transaction occurs between at least one of the IP cores and the memory device, determining an operation state of the IP core according to the result of the monitoring, and supplying the IP core with power corresponding to the operation state of the IP core.

Claims

1. A system-on-chip (SoC) connected with a memory device, the SoC comprising:

a plurality of intellectual property (IP cores);

a power management circuit configured to supply power to the IP cores; and

a transaction unit configured to control the power supplied by the power management circuit to each of the IP cores according to a data transaction between said each IP core and the memory device.

2. The SoC of claim 1, wherein the transaction unit determines:

that a particular one of the IP cores is in a normal operation mode when data transfer between the particular IP core and the memory device occurs, that the particular IP core is in a stand-by mode during a time period from an end of the data transfer to power-gating of the IP core, that the particular IP core is in a sleep mode during a period from the power gating of the particular IP core to a time when power supply resumes because of occurrence of the data transfer between the particular IP core and the memory device, and that the particular IP core is in a wake-up mode during a period from the start of resumption of the power supply to a time when the particular IP core reaches an operating power for the normal operation mode.

3. The SoC of claim 2, wherein the transaction unit controls the operating power to be supplied to the particular IP core in the normal operation mode, controls a stand-by power which is less than the operating power to be supplied to the particular IP core in the stand-by mode, interrupts power from being supplied to the particular IP core in the sleep mode, and controls power to be gradually supplied to the particular IP core from no power up to the operating power in the wake-up mode.

4. The SoC of claim 2, wherein the transaction unit counts a time period of the stand-by mode, compares the counted time period with a predetermined threshold value for the particular IP core, and controls the power supply to the particular IP core to switch the particular IP core from the stand-by mode into the sleep mode when the counted time period is at least the threshold value.

5. The SoC of claim 4, wherein the threshold values for at least two of the IP cores are different than each other.

6. The SoC of claim 4, wherein the threshold value is set to minimize latency and power consumption of the particular IP core.

7. A system-on-chip (SoC) connected with a memory device, the SoC comprising:

a plurality of intellectual property cores (IP cores);

a transaction monitor configured to monitor a data transaction between each of the IP cores and the memory device;

a period detector configured to determine an operation state of each IP core according to a monitoring result of the transaction monitor;

a control unit configured to generate a power control signal to supply said each IP core with a power corresponding to the operation state of said each IP core; and

a power management circuit configured to supply the power to said each IP core according to the power control signal.

8. The SoC of claim 7, wherein the period detector determines:

that a particular one of the IP cores is in a normal operation mode when data transfer between the particular IP core and the memory device occurs, that the particular IP core is in a stand-by mode during a period from an end of the data transfer to power-gating of the particular IP core, that the particular IP core is in a sleep mode during a period from the power gating of the IP core to a time when power supply resumes because of occurrence of data transfer between the IP core and the memory device, and that the particular IP core is in a wake-up mode during a period from the start of resumption of the power supply to a time when the particular IP core reaches an operating power for the normal operation mode.

9. The SoC of claim 8, wherein the control unit generates the power control signal to supply the operating power to the particular IP core in the normal operation mode, to supply a stand-by power lower than the operating power to the particular IP core in the stand-by mode, to interrupt power to the particular IP core in the sleep mode, and to gradually supply power to the particular IP core from no power up to the operating power in the wake-up mode.

10. The SoC of claim 8, wherein the period detector counts a time period of the stand-by mode, compares the counted time period with a predetermined threshold value, switches the particular IP core from the stand-by mode into the sleep mode when the counted period is at least the threshold value, and maintains the particular IP core in the stand-by mode when the counted period is less than the threshold value.

11. The SoC of claim 10, wherein the threshold values for at least two of the IP cores are different than each other.

12. The SoC of claim 10, wherein the threshold value is set to minimize latency and power consumption of the particular IP core.

13. A system-on-chip (SoC), comprising:

a plurality of intellectual property cores (IP cores);

a memory device comprising a main memory, a memory controller configured to control the main memory, and a memory bus configured to interface the memory controller and the IP cores to transfer data between the main memory and the IP cores;

a quality-of-service (QoS) enhancer configured to monitor a data transaction occurring in the memory bus between the IP cores and the main memory and to input and output the data in a predetermined priority order;

a period detector configured to determine an operation state of each of the IP cores according to a monitoring result indicating whether the data transaction has occurred with respect to said each IP core;

a control unit configured to generate a power control signal to supply said each IP core with a power corresponding to the operation state of said each IP core; and

a power management circuit configured to supply the power to said each IP core according to the power control signal.

14. The SoC of claim 13, wherein the QoS enhancer comprises a buffer configured to temporarily store data transferred through the memory bus, and monitors the data transaction of the buffer.

15. The SoC of claim 14, wherein the period detector determines:

that a particular one of the IP cores is in a normal operation mode when data transfer occurs in the buffer, that the particular IP core is in a stand-by mode during a period from an end of the data transfer in the buffer to power-gating of the particular IP core, that the particular IP core is in a sleep mode during a period from the power gating of the particular IP core to a time when power supply resumes because of occurrence of data transfer between the particular IP core and the memory device, and that the particular IP core is in a wake-up mode during a period from the start of resumption of power supply to a time when the particular IP core reaches an operating power for the normal operation mode.

16. The SoC of claim 15, wherein the period detector counts a period of the stand-by mode, compares the counted period with a predetermined threshold value for the particular IP core, switches the particular IP core from the stand-by mode into the sleep mode when the counted period is at least the threshold value, and maintains the particular IP core in the stand-by mode when the counted period is less than the threshold value.

17. The SoC of claim 15, wherein the control unit generates the power control signal to supply the operating power to the particular IP core in the normal operation mode, to supply a stand-by power lower than the operating power to the particular IP core in the stand-by mode, to interrupt power to the particular IP core in the sleep mode, and to gradually supply power to the particular IP core from no power up to the operating power in the wake-up mode.

18. The SoC of claim 13, wherein the power management circuit is further configured to supply power to the memory device.

19. The SoC of claim 16, wherein the threshold value is set to minimize latency and power consumption of the particular IP core.

20. A method of operating a system-on-chip (SoC) connected between a plurality of intellectual property cores (IP cores) and a memory device, the method comprising:

monitoring whether a data transaction occurs between at least one of the IP cores and the memory device;

determining an operation state of the at least one IP core according to a result of the monitoring; and

supplying the IP core with power corresponding to the operation state of the IP core.

21. The method of claim 20, wherein the determining the operation state comprises:

determining that the IP core is in a normal operation mode when data transfer between the IP core and the memory device occurs;

determining that the IP core is in a stand-by mode during a period from an end of the data transfer to power-gating of the IP core;

determining that the IP core is in a sleep mode during a period from the power gating of the IP core to a time when power supply resumes because of occurrence of data transfer between the IP core and the memory device; and

determining that the IP core is in a wake-up mode during a period from the start of resumption of the power supply to a time when the IP core reaches an operating power for the normal operation mode.

22. The method of claim 21, wherein determining that the IP core is in the sleep mode and determining that the IP core is in the wake-up mode comprise:

counting a time period of the stand-by mode;

comparing the counted period with a predetermined threshold value;

determining that the IP core is in the sleep mode when the counted time period is at least the threshold value; and

determining that the IP core is in the stand-by mode when the counted time period is less than the threshold value.

23. The method of claim 22, wherein the threshold values for at least two of the IP cores are different than each other.

24. The method of claim 22, wherein the threshold value is set to minimize latency and power consumption of the IP core.

25. The method of claim 21, wherein supplying the IP core with the power comprises:

supplying the operating power to the IP core in the normal operation mode;

supplying a stand-by power which is less than the operating power to the IP core in the stand-by mode;

interrupting power to the IP core in the sleep mode; and

gradually supplying power to the IP core from no power up to the operating power in the wake-up mode.

26. A method of operation of a device including at least two intellectual property cores (IP cores) which may communicate with a memory device, the method comprising:

monitoring data transactions between each of the IP cores and the memory device;

determining a state of each of the IP cores in response to the monitored data transactions; and

individually controlling power supplied to each of the IP cores according to their respective states.

27. The method of claim 26, wherein determining the state of each of the IP cores comprises determining, for each IP core:

whether it is in an operating state, whether it is in a standby-state;

whether it is in a sleep state, and whether it is in a wake-up state.

28. The method of claim 27, wherein determining the state of each of the IP cores comprises determining that the state of one of the IP cores is the operating state when a data transaction is performed between that one IP core and the memory device.

29. The method of claim 27, wherein determining the state of each of the IP cores comprises determining that the state of one of the IP cores is the standby state when a data transaction is not being performed between that one IP core and the memory device, and a time period which has elapsed since an immediate preceding data transaction between that one IP core and the memory device is less than a threshold.

30. The method of claim 27, wherein determining the state of each of the IP cores comprises determining that the state of one of the IP cores is the sleep state when a data transaction is not being performed between that one IP core and the memory device, and a time period which has elapsed since an immediate preceding data transaction between that one IP core and the memory device is greater than a threshold.