POWER MANAGEMENT SYSTEM AND METHOD FOR A PROCESSOR

• US 20140089699A1
• Filed: 09/27/2012
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: O'Connor, James M., Schulte, Michael, Manne, Srilatha, Lee, Jungseob
• Application Number:
  US13/628,720
• Publication Number:
  US 20140089699A1
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2350/00 Solving problems of bandwidth in display systems
• CPC Class Codes: G09G 2360/08 Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure relates to a method and apparatus for dynamically controlling power consumption by at least one processor. A power management method includes monitoring, by power control logic of the at least one processor, performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor. The method includes adjusting, by the power control logic following an execution of the repetitive workload, an operating frequency of at least one of a compute unit and a memory controller upon a determination that the at least one processor is at least one of compute-bound and memory-bound based on monitored performance data associated with the execution of the repetitive workload.

Claims

1. A power management method for at least one processor having a compute unit and a memory controller, the method comprising:

monitoring, by power control logic of the at least one processor, performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor; and

adjusting, by the power control logic following an execution of the repetitive workload, an operating frequency of at least one of the compute unit and the memory controller upon a determination by the power control logic that the at least one processor is at least one of compute-bound and memory-bound based on monitored performance data associated with the execution of the repetitive workload.

2. The method of claim 1, wherein the monitoring includes receiving an identifier associated with the repetitive workload, further comprising executing the repetitive workload upon each receipt of the identifier.

3. The method of claim 1, wherein the determination includes

determining a total workload execution time associated with the execution of the repetitive workload,

determining a percentage of the total workload execution time that at least one of a load module and a write module of the compute unit is in a stalled condition, the load module being configured to load data from the memory controller and the write module being configured to write data to the memory controller, and

comparing the percentage of the total workload execution time to a threshold percentage to determine that the at least one processor is at least one of compute-bound and memory-bound.

4. The method of claim 1, wherein the determination includes determining that the at least one processor is compute-bound based on the memory controller having unused memory bandwidth during the execution of the repetitive workload and determining that the at least one processor is memory-bound based on the compute unit being in a stalled condition during the execution of the repetitive workload.

5. The method of claim 4, wherein the adjusting includes reducing the operating frequency of the compute unit upon a determination that the at least one processor is memory-bound during the execution of the workload and reducing the operating frequency of the memory controller upon a determination that the at least one processor is compute-bound during the execution of the workload.

6. The method of claim 4, wherein the adjusting includes increasing the operating frequency of the memory controller upon a determination that the at least one processor is memory-bound during the execution of the workload and increasing the operating frequency of the compute unit upon a determination that the at least one processor is compute-bound during the execution of the workload.

7. The method of claim 1, further comprising

receiving a workload having an execution time that is less than a threshold execution time, and

executing the workload at a maximum operating frequency of the compute unit and the memory controller.

8. The method of claim 1, wherein the repetitive workload comprises at least one of a workload configured for multiple executions by the at least one processor and multiple workloads having similar workload characteristics.

9. The method of claim 1, wherein the adjusting, by the power control logic, further comprises adjusting the operation of at least one of the compute unit, the memory controller, and the memory by employing one or more of the following:

clock gating, power gating, power sloshing, and temperature sensing.

10. A power management method for at least one processor having a compute unit and a memory controller, the method comprising:

monitoring, by power control logic of the at least one processor, performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor;

determining, by the power control logic, a percentage of a total workload execution time of a first execution of the repetitive workload that at least one of a write module, a load module, and an execution module of the compute unit is in a stalled condition based on performance data associated with the first execution of the repetitive workload; and

adjusting, by the power control logic prior to a second execution of the repetitive workload, an operating frequency of at least one of the compute unit and the memory controller based on a comparison of the determined percentage with a threshold percentage.

11. The method of claim 10, wherein the adjusting includes reducing the operating frequency of the compute unit upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition exceeding a first threshold and reducing the operating frequency of the memory controller upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition being less than a second threshold.

12. The method of claim 11, wherein the first and second thresholds are based on the percentage of the total workload execution time that the execution module is in a stalled condition.

13. The method of claim 10, wherein the adjusting includes increasing the operating frequency of the memory controller upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition exceeding a first threshold and increasing the operating frequency of the compute unit upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition being less than a second threshold.

14. The method of claim 13, wherein the operating frequency of the at least one of the compute unit and the memory controller is increased based on a total power consumption of the at least one processing device during the first execution of the workload being less than a maximum power consumption threshold.

15. The method of claim 10, wherein the load module is configured to load data from the memory controller, the write module is configured to write data to the memory controller, and the execution module is configured to perform computations associated with the execution of the repetitive workload.

16. The method of claim 10, wherein the operating frequency of the at least one of the compute unit and the memory controller is adjusted by a predetermined increment following each of a plurality of successive executions of the repetitive workload based on the monitored performance data.

17. The method of claim 10, further including

detecting a performance loss of the at least processor following the second execution of the repetitive workload with the adjusted operational frequency based on the monitored performance data, and

restoring a previous operating frequency of the at least one of the compute unit and the memory controller upon the detected performance loss exceeding a performance loss threshold.

18. The method of claim 10, wherein the at least one processor includes a plurality of compute units, the method further comprising determining, by the power control logic, a minimum number of compute units of the at least one processor required for an execution of the repetitive workload based on a processing capacity of each compute unit, each compute unit being operative to execute at least one processing thread of the repetitive workload.

19. An integrated circuit comprising:

at least one processor including a memory controller and a compute unit in communication with the memory controller, the at least one processor having power control logic operative to

monitor performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor, and

adjust, following an execution of the repetitive workload by the at least one processor, an operating frequency of at least one of the compute unit and the memory controller upon a determination by the power control logic that the at least one processor is at least one of compute-bound and memory-bound based on monitored performance data associated with the execution of the repetitive workload.

20. The integrated circuit of claim 19, wherein the power control logic is further operative to receive an identifier associated with the repetitive workload, wherein the at least one processor executes the repetitive workload upon each receipt of the identifier.

21. The integrated circuit of claim 19, wherein the power control logic determines that the at least one processor is compute-bound based on the memory controller having unused memory bandwidth during the execution of the repetitive workload and determines that the at least one processor is memory-bound based on the compute unit being in a stalled condition during the execution of the repetitive workload.

22. The integrated circuit of claim 21, wherein the power control logic is operative to reduce the operating frequency of the compute unit upon a determination that the at least one processor is memory-bound during the execution of the workload and to reduce the operating frequency of the memory controller upon a determination that the at least one processor is compute-bound during the execution of the workload.

23. The integrated circuit of claim 21, wherein the power control logic is operative to increase the operating frequency of the memory controller upon a determination that the at least one processor is memory-bound during the execution of the workload and to increase the operating frequency of the compute unit upon a determination that the at least one processor is compute-bound during the execution of the workload.

24. The integrated circuit of claim 19, wherein the at least one processor is in communication with a second processor and a system memory, the memory controller is operative to access the system memory, and the second processor is operative to execute a program and to offload the repetitive workload for execution by the at least one processor, wherein the repetitive workload is associated with the program.

25. An integrated circuit comprising:

at least one processor including a memory controller and a compute unit in communication with the memory controller, the compute unit including a write module, a load module, and an execution module, the at least one processor having power control logic operative to

monitor performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor,

determine a percentage of a total workload execution time of a first execution of the repetitive workload that at least one of the write module, the load module, and the execution module of the compute unit is in a stalled condition based on performance data associated with the first execution of the repetitive workload, and

adjust, prior to a second execution of the repetitive workload, an operating frequency of at least one of the compute unit and the memory controller based on a comparison of the determined percentage with a threshold percentage.

26. The integrated circuit of claim 25, wherein the power control logic is operative to reduce the operating frequency of the compute unit upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition exceeding a first threshold and to reduce the operating frequency of the memory controller upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition being less than a second threshold.

27. The integrated circuit of claim 25, wherein the power control logic is operative to increase the operating frequency of the memory controller upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition exceeding a first threshold and to increase the operating frequency of the compute unit upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition being less than a second threshold.

28. The method of claim 27, wherein the first and second thresholds are based on the percentage of the total workload execution time that the execution module is in a stalled condition.

29. The method of claim 27, wherein the power control logic increases the operating frequency of the at least one of the compute unit and the memory controller based on a total power consumption of the at least one processor during the first execution of the workload being less than a maximum power consumption threshold.

30. The method of claim 25, wherein the load module is configured to load data from the memory controller, the write module is configured to write data to the memory controller, and the execution module is configured to perform computations associated with the execution of the repetitive workload.

31. The integrated circuit of claim 25, wherein the power control logic is further operative to

detect a performance loss of the at least processor following the second execution of the repetitive workload with the adjusted operational frequency based on the monitored performance data, and

restore a previous operating frequency of the at least one of the compute unit and the memory controller upon the detected performance loss exceeding a performance loss threshold.

32. A non-transitory computer-readable medium comprising:

executable instructions such that when executed by at least one processor cause the at least one processor to;

monitor performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor, and

adjust, following an execution of the repetitive workload by the at least one processor, an operating frequency of at least one of the compute unit and the memory controller upon a determination by the power control logic that the at least one processor is at least one of compute-bound and memory-bound based on monitored performance data associated with the execution of the repetitive workload.

33. The non-transitory computer-readable medium of claim 32, wherein the executable instructions further cause the at least one processor to:

receive an identifier associated with the repetitive workload, and

execute the repetitive workload upon each receipt of the identifier.

34. The non-transitory computer-readable medium of claim 32, wherein the executable instructions further cause the at least one processor to:

determine that the at least one processor is compute-bound based on the memory controller having unused memory bandwidth during the execution of the repetitive workload, and

determine that the at least one processor is memory-bound based on the compute unit being in a stalled condition during the execution of the repetitive workload.

35. The non-transitory computer-readable medium of claim 34, wherein the executable instructions further cause the at least one processor to:

reduce the operating frequency of the compute unit upon a determination that the at least one processor is memory-bound during the execution of the workload, and

reduce the operating frequency of the memory controller upon a determination that the at least one processor is compute-bound during the execution of the workload.

36. The non-transitory computer-readable medium of claim 34, wherein the executable instructions further cause the at least one processor to:

increase the operating frequency of the memory controller upon a determination that the at least one processor is memory-bound during the execution of the workload, and

increase the operating frequency of the compute unit upon a determination that the at least one processor is compute-bound during the execution of the workload.

37. An apparatus comprising:

a first processor operative to execute a program and to offload a repetitive workload associated with the program for execution by another processor; and

a second processor in communication with the first processor and operative to execute the repetitive workload, the second processor including a memory controller and a compute unit in communication with the memory controller, the compute unit including a write module, a load module, and an execution module, the second processor including power control logic operative to

monitor performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor,

determine a percentage of a total workload execution time of a first execution of the repetitive workload that at least one of the write module, the load module, and the execution module of the compute unit is in a stalled condition based on performance data associated with the first execution of the repetitive workload, and

adjust, prior to a second execution of the repetitive workload, an operating frequency of at least one of the compute unit and the memory controller based on a comparison of the determined percentage with a threshold percentage.

38. The apparatus of claim 37, wherein the power control logic of the second processor is operative to reduce the operating frequency of the compute unit upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition exceeding a first threshold and to reduce the operating frequency of the memory controller upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition being less than a second threshold.

39. The method of claim 38, wherein the first and second thresholds are based on the percentage of the total workload execution time that the execution module is in a stalled condition.

40. The apparatus of claim 37, wherein the power control logic of the second processor is operative to increase the operating frequency of the memory controller upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition exceeding a first threshold and to increase the operating frequency of the compute unit upon the percentage of the total workload execution time that at least one of the write module and the load module is in a stalled condition being less than a second threshold.

41. The apparatus of claim 40, wherein the power control logic of the second processor increases the operating frequency of the at least one of the compute unit and the memory controller based on a total power consumption of the second processor during the first execution of the workload being less than a maximum power consumption threshold.

42. The apparatus of claim 37, wherein the load module is configured to load data from the memory controller, the write module is configured to write data to the memory controller, and the execution module is configured to perform computations associated with the execution of the repetitive workload.

43. The apparatus of claim 37, wherein the power control logic of the second processor is further operative to

detect a performance loss of the second processor following the second execution of the repetitive workload with the adjusted operational frequency based on the monitored performance data, and

restore a previous operating frequency of the at least one of the compute unit and the memory controller upon the detected performance loss exceeding a performance loss threshold.