SERIAL ADVANCED TECHNOLOGY ATTACHMENT DUAL IN-LINE MEMORY MODULE DEVICE HAVING TESTING CIRCUIT FOR CAPACITOR

• US 20140089739A1
• Filed: 10/30/2012
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Abandoned Application

• Current Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Guo-Yi Chen, Xiao-Gang Yin
• Inventors: YIN, XIAO-GANG, CHEN, GUO-YI
• Application Number:
  US13/663,639
• Publication Number:
  US 20140089739A1
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A serial advanced technology attachment dual in-line memory module device includes a capacitor to be tested, a control chip, a display device, a testing chip, and a selecting chip. Voltage pins of the testing chip and the selecting chip are connected to a power source. A testing pin of the testing chip is connected to the capacitor. A first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip. A second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip. A third I/O pin of the selecting chip is connected to an input pin of the control chip. A fourth I/O pin of the selecting chip is connected to an output pin of the control chip. A fifth I/O pin of the selecting chip is connected to the display device.

Claims

1. A serial advanced technology attachment dual in-line memory module (SATA DIMM) device, comprising:

a capacitor;

a control chip;

a display device;

a testing chip storing a preset voltage, wherein a voltage pin of the testing chip is connected to a power source, a testing pin of the testing chip is connected to the capacitor; and

a selecting chip, wherein a voltage pin of the selecting chip is connected to the power source, a first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip, a second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip, a third I/O pin of the selecting chip is connected to an input pin of the control chip, a fourth I/O pin of the selecting chip is connected to an output pin of the control chip, a fifth I/O pin of the selecting chip is connected to the display device;

wherein when the SATA DIMM device is powered on, the control chip outputs a first signal to the fourth I/O pin of the selecting chip through the output pin of the control chip, the fourth I/O pin and the first I/O pin of the selecting chip are connected and output the first signal to the testing chip, the third I/O pin and the second I/O pin of the selecting chip are connected, the testing chip receives the first signal through the first I/O pin and measures a voltage of the capacitor through the testing pin and compares the measured voltage with the preset voltage, upon a condition that the testing voltage is equal to or greater than the preset voltage, the testing chip outputs a testing pass signal to the control chip through the second I/O pin of the testing chip, the second I/O pin of the selecting chip, and the third I/O pin of the selecting chip, the control chip receives the testing pass signal and outputs a second signal to the fourth I/O pin of the selecting chip through the output pin of the control chip, the third I/O pin of the selecting chip and the fifth I/O pin of the selecting chip are connected, the control chip controls the display device to display a testing result to show that the capacitor is qualified;

upon a condition that the measured voltage is less than the preset voltage, the testing chip outputs a testing fail signal to the control chip through the second I/O pin of the testing chip, the second I/O pin of the selecting chip, and the third I/O pin of the selecting chip, the control chip receives the testing fail signal and outputs a third signal to the fourth I/O pin of the selecting chip through the output pin of the control chip, the third I/O pin and the fifth I/O pin of the selecting chip are connected, the control chip controls the display device to display a testing result to show that the capacitor is unqualified.

2. The SATA DIMM device of claim 1, further comprising first to ninth resistors, wherein the first resistor is connected between the second I/O pin of the testing chip and the voltage pin of the testing chip, the second resistor is connected between the third I/O pin of the testing chip and the voltage pin of the testing chip, the third resistor is connected between the testing pin of the testing chip and the capacitor to be tested, the fourth resistor is connected between the first I/O pin of the testing chip and ground, the fifth resistor is connected between the fifth I/O pin of the testing chip and ground, the sixth resistor is connected between the input pin of the control chip and the power source, the seventh resistor is connected between the input pin of the control chip and ground, the eighth resistor is connected between the third I/O pin of the selecting chip and the input pin of the control chip, the ninth resistor is connected between the output pin of the control chip and the fourth I/O pin of the selecting chip.

3. The SATA DIMM device of claim 1, further comprising first to fifth capacitors, wherein the first capacitor is connected between the voltage pin of the testing chip and ground, the second capacitor is connected between the fourth I/O pin of the testing chip and ground, the third capacitor is connected between the fifth resistor and ground, the fourth capacitor is connected between the voltage pin of the selecting chip and ground, the fifth capacitor is connected between the fourth I/O pin of the selecting chip and ground.