TEST COVERAGE OF INTEGRATED CIRCUITS WITH TEST VECTOR INPUT SPREADING

• US 20140089750A1
• Filed: 09/27/2012
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Douskey, Steven M., Fitch, Ryan A., Hamilton, Michael J., Kaufer, Amanda R.
• Granted Patent: US 9,116,205 B2
• Time in Patent Office: Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts

Abstract

An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).

Claims

1. A circuit comprising:

one or more scan channels; and

one or more switching devices coupled to the one or more scan channels, wherein the one or more switching devices are adapted to couple a scan channel with one of one or more test vector inputs, the one of one or more test vector inputs is selected by the one or more switching devices based on one or more test mode signals received by the one or more switching devices.

2. The circuit of claim 1, wherein the one or more switching devices couple each scan channel with a unique test vector encode, the test vector encode includes one or more test vectors, each test vector is signaled by the one or more switching devices based on the test mode of one or more test modes received by the one or more switching devices.

3. The circuit of claim 1, wherein the one or more switching devices couple each scan channel with a unique inverted test vector encode, the test vector encode includes one or more inverted test vectors, each test vector is signaled by the one or more switching devices based on a test mode of one or more test modes received by the one or more switching devices.

4. The circuit of claim 2, wherein the one or more switching devices adapts to couple selected test vector encodes with the one or more scan channels, the selected test vector encodes are from a plurality of all possible test vector encode combinations, each selected vector encode selected for producing couples of test vectors with scan channels.

5. The circuit of claim 2, wherein a test vector encode for the scan channel is different than another test vector encode for another scan channel for a plurality of test modes.

6. The circuit in claim 1, wherein the number of scan channels is equal to or greater than the number of switching devices.

7. The circuit in claim 2, wherein the one or more switching devices controls a select group of test vectors from a larger group of test vectors to a plurality of scan channels, a select group of test vectors combined to produce coupling of test vectors with scan channels.

8. The integrated circuit in claim 1, wherein the switching device is a multiplexer.

9-14. -14. (canceled)

15. A circuit, comprising:

one or more scan channels, wherein each scan channel is coupled to an output of one or more switching devices which is further coupled to one or more test vector sources;

a control mechanism, wherein the control mechanism sends a test mode signal to the one or more switching devices; and

one or more switching devices, wherein the one or more switching devices selects one or more test vector sources from the one or more test vector sources to the one or more scan channels in response to the test mode signal from the control mechanism according to a testing scheme.

16. The circuit of claim 15, wherein the testing scheme selectively inverts a scan channel.

17. The circuit of claim 15, wherein the testing scheme is developed using trinary patterns.

18. The circuit of claim 15, wherein the testing scheme groups three or more Scan Data Ins (SDIs) and selects a plurality of scan channels for the SDIs across different test modes.

19. The integrated circuit of claim 15, wherein the testing scheme increases a number of combinations of the SDIs and the scan channels.

20. The integrated circuit of claim 15, wherein the test vector originates from a pattern generator.