SELF-ALIGNED STRUCTURES AND METHODS FOR ASYMMETRIC GAN TRANSISTORS & ENHANCEMENT MODE OPERATION

• US 20140091308A1
• Filed: 09/28/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Niti Goel, Ravi Pillarisetty, Robert S. Chau, Sanaz Kabehie, Seung Hoon Sung
• Inventors: THEN, Han Wui, RADOSAVLJEVIC, Marko, PILLARISETTY, Ravi, CHAU, Robert S., DASGUPTA, Sansaptak, MUKHERJEE, Niloy, GOEL, Niti, KABEHIE, Sanaz, SUNG, Seung Hoon
• Granted Patent: US 9,099,490 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/2233 Diffusion into or out of AIIIBV compounds
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/2654 in AIIIBV compounds
• CPC Class Codes: H01L 21/26546 of electrically active species
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Claims

1. A high electron mobility field effect transistor (HEMT), comprising:

a group III-N semiconductor channel layer disposed over a substrate;

a gate stack disposed over a first region of the channel layer;

a source region in contact with the channel layer on a first side of the gate stack;

a drain region in contact with the channel layer on a second side of the gate stack opposite the source region;

a dielectric liner disposed over a first length of a semiconductor barrier layer between the source region and the gate stack, and disposed over a second length of the semiconductor barrier layer between the drain region and the gate stack that is larger than the first length, wherein the dielectric liner comprises first liner sidewalls on opposite sides of the gate stack, and further comprises a second liner sidewall defining the first or second length with a filler dielectric disposed between the first liner sidewalls and the second liner sidewall.

2. The HEMT of claim 1, wherein the dielectric liner further comprises a third liner sidewall defining the other of the first or second length with the filler dielectric disposed between the first liner sidewalls and the third liner sidewall.

3. The HEMT of claim 1, wherein the dielectric liner comprises a material having a higher dielectric constant than the filler dielectric, and wherein the gate stack further comprises a gate dielectric layer including a metal oxide that extends between the first liner sidewalls and along the entire lengths of the first liner sidewalls, and extends over the filler dielectric.

4. The HEMT of claim 3, wherein the gate dielectric layer is disposed directly on the second liner sidewall.

5. The HEMT of claim 1, wherein the source and drain regions each comprise InGaN doped n-type to at least 1e19 cm⁻

3.

6. The HEMT of claim 1, wherein the channel layer is GaN, and wherein semiconductor barrier layer comprises at least one of Al_zGa_1-zN, Al_wIn_1-wN, AlN, or a quarternary of AlInGaN.

7. The HEMT of claim 1, wherein a first region of the semiconductor barrier layer disposed between the gate stack and the channel layer is at least one of:

a lesser thickness than a second region of the semiconductor barrier layer disposed between the dielectric liner and the channel layer, or

fluorine doped.

8. The HEMT of claim 1, wherein the first region of the semiconductor barrier layer is fluorine doped to between 1e17 cm⁻

3 and 1e18 cm<sup>−

3</sup>.

13. A mobile computing device, comprising:

a touchscreen;

a battery;

an antenna;

a DC-to-DC converter coupled to the battery; and

a wireless transmitter further including a power amplifier (PA), wherein at least one of the DC-to-DC converter and the PA comprises the HEMT as in claim 1 or 9.

9. A high electron mobility transistor (HEMT), comprising:

a gate electrode disposed between a source semiconductor region and a drain semiconductor region;

a gate dielectric disposed below the gate electrode;

a group III-N channel layer disposed below the gate dielectric; and

a semiconductor barrier layer disposed between the channel layer and the gate dielectric, wherein the semiconductor barrier layer is fluorine doped.

10. The HEMT of claim 9, wherein the semiconductor barrier layer comprises at least one of Al_zGa_1-zN, Al_wIn_1-wN, or AlN and is fluorine doped to between 1e17 cm⁻

3 and 1e18 cm<sup>−

3</sup> in a first region disposed between the channel layer.

11. The HEMT of claim 10, wherein the gate dielectric layer further comprises:

a base dielectric layer of a first composition disposed directly on the fluorine doped semiconductor barrier layer; and

a top dielectric layer of a second composition disposed directly on the base dielectric layer.

12. The HEMT of claim 9, further comprising a dielectric liner disposed over a first length of the semiconductor barrier layer between the source region and the gate dielectric, and disposed over a second length of the semiconductor barrier layer between the drain region and the gate dielectric that is larger than the first length, wherein the dielectric liner comprises first liner sidewalls on opposite sides of the gate dielectric, and further comprises a second liner sidewall defining the first or second length with a filler dielectric disposed between the first liner sidewalls and the second liner sidewall.

14. A method of forming an asymmetric high electron mobility transistor (HEMT), the method comprising:

depositing a sacrificial material over a substrate comprising a group III-N channel layer;

etching at least one trench to form a mandrel of the sacrificial material spaced apart by a first length and a second length, different from the first, from peripheral regions of the sacrificial material;

conformally depositing a dielectric liner into the at least one trench and over the mandrel;

depositing a bulk dielectric over the dielectric liner to fill the at least one trench;

etching through the bulk dielectric and dielectric liner to expose the peripheral regions of the sacrificial material;

etching the peripheral regions of the sacrificial material selectively to the dielectric liner to expose a semiconductor channel layer disposed at the periphery of the at least one trench;

forming semiconductor source and drain regions in contact with the exposed semiconductor channel layer;

etching through the bulk dielectric and dielectric liner to expose the mandrel; and

replacing the mandrel with a gate stack.

15. The method of claim 14, wherein depositing the sacrificial materialfurther comprises depositing a dielectric, wherein conformally depositing the dielectric liner further comprises depositing a material including a metal oxide, and wherein depositing the bulk dielectric further comprises depositing a dielectric with a lower dielectric constant than that of the dielectric liner.

16. The method of claim 15, wherein etching through the bulk dielectric and dielectric liner further comprises:

masking a region encompassing the mandrel and at least a portion of the at least one trench; and

anisotropically etching the bulk dielectric and dielectric liner unprotected by the masking.

17. The method of claim 16, wherein etching the peripheral regions of the sacrificial material to expose a semiconductor channel layer further comprises:

isotropically etching the sacrificial material;

etching a semiconductor barrier layer disposed over the channel layer; and

recessing the channel layer surface with an isotropic etch to undercut an interfacial layer of the channel layer in contact with the barrier layer.

18. The method of claim 14, wherein forming the semiconductor source and drain regions further comprises conformally growing a heavily n-type doped III-N material with a metalorganic precursor.

19. The method of claim 18, wherein the heavily doped III-N material comprises InGaN doped to at least 1e19 cm⁻

3.

20. The method of claim 14, wherein etching through the bulk dielectric and dielectric liner to expose the mandrel further comprises anisotropically etching a portion of the bulk dielectric and dielectric liner disposed over the mandrel;

and

wherein replacing the mandrel with a gate stack further comprises;

etching the sacrificial material selectively to the dielectric liner to expose and underlying semiconductor layer;

conformally depositing a gate dielectric layer over the channel layer and over the dielectric liner; and

depositing a gate metal over the gate dielectric layer.

21. The method of claim 14, further comprising doping a semiconductor barrier layer disposed over the channel layer with fluorine by implantation or exposure to a plasma of a fluorinated source gas.

22. The method of claim 21, wherein replacing the mandrel with a gate stack further comprises:

etching the sacrificial material selectively to the dielectric liner to expose the semiconductor barrier layer;

conformally depositing a base gate dielectric layer directly on the fluorine doped semiconductor barrier layer;

conformally depositing a top gate dielectric layer directly on the base gate dielectric layer; and

depositing a gate metal over the top gate dielectric layer.

23. A method of forming a high electron mobility transistor (HEMT), the method comprising:

forming a source region and a drain region in contact with a III-N semiconductor channel region disposed over a substrate;

fluorine doping a semiconductor barrier layer disposed on the channel region;

depositing a gate dielectric over the barrier layer; and

depositing a gate electrode over the gate dielectric.

24. The method of claim 23, wherein the fluorine doping further comprises fluorine doping at least a portion of the barrier layer to between 1e17 and 1e18 cm⁻

3.

25. The method of claim 23, wherein the fluorine doping further comprises:

implanting or exposing the semiconductor barrier layer to a plasma of a fluorinated source gas.

26. The method of claim 25, wherein the fluorine doping comprises exposing the semiconductor to a plasma of a fluorinated source gas.

27. The method of claim 23, wherein depositing the gate dielectric further comprises:

conformally depositing a base gate dielectric layer onto the barrier layer at a first temperature; and

conformally depositing a top gate dielectric layer onto the base gate dielectric layer at a second temperature, higher than the first.