SEMICONDUCTOR DEVICE USING 2-DIMENSIONAL ELECTRON GAS AND 2-DIMENSIONAL HOLE GAS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

• US 20140091310A1
• Filed: 04/10/2013
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Jai-kwang, Oh, Jae-joon, Jeon, Woo-chul
• Granted Patent: US 9,214,517 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A semiconductor device includes a first compound semiconductor layer on a substrate, first through third electrodes spaced apart from each other on the first compound semiconductor layer, a second compound semiconductor layer on the first compound semiconductor layer between the first through third electrodes, a third compound semiconductor layer on the second compound semiconductor layer between the first and second electrodes, a first gate electrode on the third compound semiconductor layer, a fourth compound semiconductor layer having a smaller thickness than the third compound semiconductor layer on a portion of the second compound semiconductor layer between the second and third electrodes, and a second gate electrode on the fourth compound semiconductor layer. The first compound semiconductor layer between the second and third electrodes includes a 2-dimensional electron gas (2DEG) and the third compound semiconductor layer includes a 2-dimensional hole gas (2DHG).

Claims

1. A semiconductor device comprising:

a first compound semiconductor layer on a substrate;

first through third electrodes on the first compound semiconductor layer, the first through third electrodes spaced apart from each other and the first compound semiconductor layer between the second and third electrodes including a 2-dimensional electron gas (2DEG);

a second compound semiconductor layer on the first compound semiconductor layer between the first through third electrodes, the second compound semiconductor layer having a higher band gap than the first compound semiconductor layer;

a third compound semiconductor layer on the second compound semiconductor layer between the first and second electrodes, the third compound semiconductor layer including a 2-dimensional hole gas (2DHG);

a first gate electrode on the third compound semiconductor layer;

a fourth compound semiconductor layer on a part of the second compound semiconductor layer between the second and third electrodes, the fourth compound semiconductor layer having a smaller thickness than the third compound semiconductor layer; and

a second gate electrode on the fourth compound semiconductor layer, the second gate electrode connected to the first gate electrode through a first wire.

2. The semiconductor device of claim 1, further comprising:

a second wire connecting the first and third electrodes.

3. The semiconductor device of claim 1, wherein band gaps of the third and fourth compound semiconductor layers are smaller than the band gap of the second compound semiconductor layer.

4. The semiconductor device of claim 3, wherein the third and fourth compound semiconductor layers are formed of one of same and different compound semiconductors.

5. The semiconductor device of claim 3, wherein the third and fourth compound semiconductor layers include p-gallium nitride (GaN) layers.

6. The semiconductor device of claim 1, wherein the first compound semiconductor layer includes a Group III-V compound semiconductor layer.

7. A semiconductor device comprising:

an n-type switching device on a substrate, the n-type switching device including a first gate and a 2-dimensional electron gas (2DEG) as a channel carrier; and

a p-type switching device on the substrate, the p-type switching device including a second gate and a 2-dimensional hole gas (2DHG) as a channel carrier,

wherein the n- and p-type switching devices include a common electrode, and the first and second gates of the n- and p-type switching devices are connected to each other through a first wire.

8. The semiconductor device of claim 7, wherein a drain of the n-type switching device and a drain of the p-type switching device are connected to each other through a second wire.

9. The semiconductor device of claim 7, wherein the p-type switching device is a freewheeling diode (FRD).

10. The semiconductor device of claim 7, wherein the n-type switching device comprises:

first and second compound semiconductor layers sequentially stacked on the substrate;

a fourth compound semiconductor layer on a portion of the second compound semiconductor layer;

the first gate on the fourth compound semiconductor layer; and

source and drain electrodes on the first compound semiconductor layer, the source and drain electrodes spaced apart from the first gate and the fourth compound semiconductor layer,

wherein a band gap of the second compound semiconductor layer is higher than band gaps of the first and fourth compound semiconductor layers, and

wherein the 2DEG is included in the first compound semiconductor layer around the fourth compound semiconductor layer.

11. The semiconductor device of claim 7, wherein the p-type switching device comprises:

first through third compound semiconductor layers sequentially stacked on the substrate;

the second gate on the third compound semiconductor layer; and

source and drain electrodes on the first compound semiconductor layer and contacting the second and third compound semiconductor layers,

wherein a band gap of the second compound semiconductor layer is higher than band gaps of the first and third compound semiconductor layers, and

wherein the 2DHG is included in the third compound semiconductor layer.

12. A method of manufacturing a semiconductor device, the method comprising:

sequentially forming a first compound semiconductor layer, a second compound semiconductor layer and a preliminary compound semiconductor layer on a substrate, the preliminary compound semiconductor layer formed to a thickness at which a 2-dimensional hole gas (2DHG) is shown;

sequentially patterning the preliminary compound semiconductor layer and the second compound semiconductor layer to expose first through third regions of the first compound semiconductor layer, the first through third regions being separate from each other;

forming first through third electrodes respectively on the first through third regions;

forming third and fourth compound semiconductor layers by decreasing a thickness of one of a region of the preliminary compound semiconductor layer between the first and second electrodes and a region of the preliminary compound semiconductor layer between the second and third electrodes, the third compound semiconductor layer having a greater thickness than the fourth compound semiconductor layer;

forming a 2-dimensional electron gas (2DEG) in the first compound semiconductor layer by removing a portion of the fourth compound semiconductor layer;

forming first and second gate electrodes respectively on the third and fourth compound semiconductor layers; and

connecting the first and second gate electrodes through a first wire.

13. The method of claim 12, wherein the second electrode is between the first and second gate electrodes, the method further comprising:

connecting the first and third electrodes through a second wire.

14. The method of claim 13, wherein the connecting the first and second gate electrodes comprises:

forming a first interlayer insulation layer covering the first through third electrodes, the third and fourth compound semiconductor layers, and the first and second gate electrodes;

forming first and second contact holes in the first interlayer insulation layer, the first contact hole partially exposing the first gate electrode and the second contact hole partially exposing the second gate electrode;

forming a conductive film filling the first and second contact holes in the first interlayer insulation layer; and

patterning the conductive film into the first wire.

15. The method of claim 14, wherein the connecting the first and third electrodes comprises:

forming a second interlayer insulation layer covering the first interlayer insulation layer and the first wire;

forming third and fourth contact holes in the first and second interlayer insulation layers, the third contact hole partially exposing the first electrode and the fourth contact hole partially exposing the third electrode; and

forming the second wire filing the third and fourth contact holes in the first and second interlayer insulation layers.

16. A method of forming a semiconductor device, the method comprising:

sequentially forming a first compound semiconductor layer, a second compound semiconductor layer, and a preliminary compound semiconductor layer on a substrate, the preliminary compound semiconductor layer formed to a thickness at which a 2-dimensional hole gas (2DHG) is shown;

decreasing a thickness of a portion of the preliminary compound semiconductor layer;

forming third and fourth compound semiconductor layers by separating the portion of the preliminary compound semiconductor layer having the decreased thickness from another portion of the preliminary compound semiconductor layer having a greater thickness, the forming the third and fourth compound semiconductor layers exposing first through third regions of the first compound semiconductor layer, the first through third regions being separate from each other;

forming first through third electrodes respectively on the first through third regions;

forming a 2-dimensional electron gas (2DEG) in the first compound semiconductor layer by removing a portion of the fourth compound semiconductor layer;

forming first and second gate electrodes respectively on the third and fourth compound semiconductor layers; and

connecting the first and second gate electrodes through a first wire.

17. The method of claim 16, wherein the second electrode is between the first and second gate electrodes, the method further comprising:

connecting the first and third electrodes through a second wire.

18. The method of claim 17, wherein the connecting the first and second gate electrodes comprises:

forming a first interlayer insulation layer covering the first through third electrodes, the third and fourth compound semiconductor layers, and the first and second gate electrodes;

forming first and second contact holes in the first interlayer insulation layer, the first contact hole partially exposing the first gate electrode and the second contact hole partially exposing the second gate electrode;

forming a conductive film filling the first and second contact holes in the first interlayer insulation layer; and

patterning the conductive film into the first wire.

19. The method of claim 18, wherein the connecting the first and third electrodes comprises:

forming a second interlayer insulation layer covering the first interlayer insulation layer and the first wire;

forming third and fourth contact holes in the first and second interlayer insulation layers, the third contact hole partially exposing the first electrode and the fourth contact hole partially exposing the third electrode; and

forming the second wire filling the third and fourth contact holes in the first and second interlayer insulation layers.

20. A method of manufacturing a semiconductor device, the method comprising:

forming a first compound semiconductor layer on a substrate;

forming first through third electrodes on the first compound semiconductor layer, the first through third electrodes spaced apart from each other;

sequentially forming a second compound semiconductor layer and a third compound semiconductor layer on the first compound semiconductor layer between the first and second electrodes, and sequentially forming the second compound semiconductor layer and a fourth compound semiconductor layer on the first compound semiconductor layer between the second and third electrodes, the third and fourth compound semiconductor layers formed to a thickness at which a 2-dimensional hole gas (2DHG) is shown;

decreasing a thickness of one of the third and fourth compound semiconductor layers;

forming a 2-dimensional electron gas (2DEG) in the first compound semiconductor layer by removing a portion of the one of the third and fourth compound semiconductor layers having the decreased thickness;

after the decreasing the thickness, forming first and second gate electrodes respectively on the third and fourth compound semiconductor layers; and

connecting the first and second gate electrodes through a first wire.

21. The method of claim 20, wherein the second electrode is between the first and second gate electrodes, the method further comprising:

connecting the first and third electrodes through a second wire.