TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S)

• US 20140091360A1
• Filed: 09/28/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Gilbert Dewey, Han Wui Then, Jack T. Kavalieros, Marko Radosavljevic, Matthew V. Metz, Niloy Mukherjee, Niti Goel, Ravi Pillarisetty, Robert S. Chau, Seung Hoon Sung, Van H. Le, Willy Rachmady
• Inventors: PILLARISETTY, Ravi, SUNG, Seung Hoon, GOEL, Niti, DASGUPTA, Sansaptak, RADOSAVLJEVIC, Marko, DEWEY, Gilbert, THEN, Han Wui, MUKHERJEE, Niloy, CHAU, Robert S., KAVALIEROS, Jack T., LE, Van H., RACHMADY, Willy, METZ, Matthew V.
• Granted Patent: US 8,765,563 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 : the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

Claims

1. A method of forming a heteroepitaxial device layer on a substrate, the method comprising:

receiving a substrate with a semiconductor seeding surface;

forming a hardmask fin over the seeding surface;

forming an isolation region adjacent the hardmask fin;

forming a trench with the seeding surface at the bottom of the trench by removing the hardmask fin; and

epitaxially growing a semiconductor layer within the trench, the semiconductor layer having at least one of a lattice constant mismatch or CTE mismatch with the semiconductor seeding surface.

2. The method of claim 1, wherein forming the hardmask fin further comprises depositing a polycrystalline silicon or a silicon nitride layer over the seeding surface;

and patterning the polycrystalline silicon or silicon nitride layer with an anisotropic etch.

3. The method of claim 2, wherein forming the hardmask fin further comprises depositing an etch stop layer directly on the seeding surface and depositing the polycrystalline silicon or a silicon nitride layer over the oxide layer.

4. The method of claim 2, wherein the anisotropic etch forms vertical sidewalls or slightly positively sloped sidewalls, and wherein the hardmask fin has an aspect ratio of at least 5:

1.

5. The method of claim 1, wherein forming the isolation region further comprises:

depositing an isolation dielectric layer over the hardmask fin, and

planarizing the isolation dielectric layer to expose a top surface of the hardmask fin.

6. The method of claim 5, wherein forming the isolation region further comprises:

etching a portion of the substrate adjacent to the hardmask fin to recess the substrate portion not protected by the hardmask fin relative to the seeding surface; and

depositing the isolation dielectric layer over the recessed substrate surface.

7. The method of claim 1, further comprising:

planarizing a top surface of the epitaxial device layer with the isolation region; and

recessing the isolation region relative to a top surface of the epitaxial device layer to form a non-planar semiconductor body comprising the epitaxial device layer with the isolation region adjacent to the non-planar semiconductor body.

8. The method of claim of claim 7, further comprising:

forming a gate dielectric and a gate electrode over at least two opposite sides of the epitaxial device layer for control of carrier conduction between source and drain regions coupled to the device layer.

9. The method of claim 8, wherein the epitaxial device layer comprises Ge or a III-V binary, ternary, or quaternary semiconductor alloy, and wherein forming the gate dielectric and the gate electrode further comprises etching a sacrificial semiconductor layer disposed between the seeding surface and the epitaxial device layer to expose a bottom surface of the epitaxial device layer;

and backfilling the gate dielectric and gate electrode over the bottom surface.

10. A non-planar field effect transistor (FET) disposed over a silicon substrate, the non-planar FET comprising:

a source region and a drain region with a non-silicon semiconductor channel disposed there between and over a planar semiconductor seeding surface having a composition other than that of the non-silicon semiconductor channel, the planar semiconductor seeding surface being a top surface of a semiconductor mesa surrounded by isolation dielectric;

a gate dielectric layer and a gate electrode layer disposed over the non-silicon semiconductor channel.

11. The non-planar FET of claim 10, wherein the non-silicon semiconductor channel is Ge, or a III-V binary ternary or quaternary compound semiconductor alloy, and wherein a center the channel is aligned with a center of the planar semiconductor seeding surface.

12. The non-planar FET of claim 11, wherein a bottom surface of the isolation dielectric is in contact with a semiconductor surface recessed below the seeding surface.

13. The non-planar FET of claim 12, wherein the seeding surface is recessed below a top surface of the dielectric isolation.

14. The non-planar FET of claim 12, wherein the non-silicon semiconductor channel is one layer of a semiconductor stack having a top surface disposed a distance from the seeding surface at least three times a minimum lateral dimension of the seeding surface.

20. A mobile computing platform comprising:

an integrated circuit comprising the non-planar FET of claim 10 or the CMOS device of claim 16,

a display screen; and

a wireless transceiver.

15. A CMOS device disposed over a silicon substrate, the CMOS device comprising:

a pMOS device having;

a first source region and a first drain region with a Ge semiconductor channel disposed there between and disposed over a first planar semiconductor seeding surface having a composition other than that of the channel, the first planar semiconductor seeding surface being a top surface of

a first semiconductor mesa surrounded by isolation dielectric; and

a first gate dielectric layer and a first gate electrode layer disposed over the Ge semiconductor channel; and

an nMOS device having;

a second source region and a second drain region with a III-V semiconductor channel disposed there between and disposed over a second planar semiconductor seeding surface having a composition other than that of the channel, the second planar semiconductor seeding surface being a top surface of a second semiconductor mesa surrounded by the isolation dielectric; and

a second gate dielectric layer and a second gate electrode layer disposed over the III-V semiconductor channel.

16. The CMOS device of claim 15, wherein the Ge semiconductor channel has a top surface disposed a first distance from the seeding surface and the III-V semiconductor channel has a top surface disposed a second distance from the seeding surface, different the first distance.

17. The CMOS device of claim 15, wherein a center the Ge semiconductor channel is aligned with a center of the first planar semiconductor seeding surface, and wherein a center the III-V semiconductor channel is aligned with a center of the second planar semiconductor seeding surface.

18. The CMOS device of claim 17, wherein the first and second seeding surfaces are recessed below a top surface of the isolation dielectric.

19. The CMOS device of claim 15, wherein the first and second gate dielectrics wrap-completely around surfaces of the semiconductor channels extending between the sources and drains.