COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20140091365A1
• Filed: 09/20/2013
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Transphorm Japan, Inc. (Kohlberg Kravis Roberts & Company LP)
• Original Assignee: Fujitsu Limited, Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Kikkawa, Toshihide, Nukui, Kenji
• Granted Patent: US 9,142,658 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons.

Claims

1. A compound semiconductor device comprising:

a compound semiconductor layer; and

a pair of electrodes formed on an upper side the compound semiconductor layer,

wherein one of the pair of electrodes has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the other of the pair of electrodes being more apart from the transit electrons.

2. The compound semiconductor device according to claim 1, wherein, in the one of the pair of electrodes, a side surface coupling predetermined adjacent two of the bottom surfaces out of the contact surfaces is in a tapered shape whose portion more apart from the other of the pair of electrodes becomes closer to the transit electrode.

3. The compound semiconductor device according to claim 1, further comprising

a protective insulating film covering the compound semiconductor layer,

wherein, in the one of the pair of electrodes, a contact side surface close to the other of the pair of electrodes out of contact side surfaces with the protective insulating film is coupled to the bottom surface.

4. The compound semiconductor device according to claim 1,

wherein the compound semiconductor layer has an electron transit layer in which the transit electrons are generated and an electron supply layer formed above the electron transit layer, and

wherein the pair of electrodes are in contact with the electron supply layer and not in contact with the electron transit layer.

5. The compound semiconductor device according to claim 1, further comprising:

another electrode formed between the pair of electrodes, above the compound semiconductor layer; and

a p-type semiconductor layer formed between the compound semiconductor layer and the other electrode.

6. A method of manufacturing a compound semiconductor device comprising:

forming a compound semiconductor layer; and

forming a pair of electrodes on an upper side the compound semiconductor layer,

wherein one of the pair of electrodes has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the other of the pair of electrodes being more apart from the transit electrons.

7. The method of manufacturing the compound semiconductor device according to claim 6, wherein, in the one of the pair of electrodes, a side surface coupling predetermined adjacent two of the bottom surfaces out of the contact surfaces is in a tapered shape whose portion more apart from the other of the pair of electrodes becomes closer to the transit electrode.

8. The method of manufacturing the compound semiconductor device according to claim 6, further comprising

forming a protective insulating film covering the compound semiconductor layer,

wherein, in the one of the pair of electrodes, a contact side surface close to the other of the pair of electrodes out of contact side surfaces with the protective insulating film is coupled to the bottom surface.

9. The method of manufacturing the compound semiconductor device according to claim 6,

wherein the compound semiconductor layer has an electron transit layer in which the transit electrons are generated and an electron supply layer formed above the electron transit layer, and

wherein the pair of electrodes are in contact with the electron supply layer and not in contact with the electron transit layer.

10. The method of manufacturing the compound semiconductor device according to claim 6, further comprising:

forming another electrode between the pair of electrodes, above the compound semiconductor layer; and

forming a p-type semiconductor layer between the compound semiconductor layer and the other electrode.

11. A power supply circuit comprising:

a transformer; and

a high-voltage circuit and a low-voltage circuit sandwiching the transformer, the high-voltage circuit comprising

a transistor, the transistor comprising;

a compound semiconductor layer; and

a pair of electrodes formed on an upper side the compound semiconductor layer,

wherein one of the pair of electrodes has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the other of the pair of electrodes being more apart from the transit electrons.