Split-Gate Memory Cell With Substrate Stressor Region, And Method Of Making Same

• US 20140091382A1
• Filed: 09/28/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tadayoni, Mandana, Do, Nhan
• Granted Patent: US 9,018,690 B2
• Time in Patent Office: Days
• US Class Current: 257/320
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

Claims

1. A memory device, comprising:

a substrate of semiconductor material of a first conductivity type;

first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween;

a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region;

a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region; and

a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

2. The memory device of claim 1, wherein the second gate has a first portion laterally adjacent to and insulated from the floating gate, and a second portion that extends up and over, and insulated from, the floating gate.

3. The memory device of claim 1, further comprising:

a conductive program/erase gate laterally to one side of, and insulated from, the floating gate, wherein the program/erase gate is disposed at least partially over and insulated from the first region; and

the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.

4. The memory device of claim 1, further comprising:

a conductive control gate over and insulated from the floating gate;

a conductive erase gate laterally to one side of, and insulated from, the floating gate, wherein the erase gate is disposed at least partially over and insulated from the first region; and

the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.

5. The memory device of claim 1, wherein the stressor region is disposed underneath a surface of the substrate such that a surface portion of the substrate over the stressor region is a strained silicon layer.

6. A method of forming a memory device, comprising:

providing a substrate of semiconductor material of a first conductivity type;

forming first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, wherein the channel region has first and second portions;

forming a stressor region of embedded silicon carbide in the substrate;

forming a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and the first portion of the channel region; and

forming a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from the second portion of the channel region and over the stressor region.

7. The method of claim 6, wherein the second gate has a first portion laterally adjacent to and insulated from the floating gate, and a second portion that extends up and over, and insulated from, the floating gate.

8. The method of claim 6, further comprising:

forming a conductive program/erase gate laterally to one side of, and insulated from, the floating gate, wherein the program/erase gate is disposed at least partially over and insulated from the first region; and

the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.

9. The method of claim 6, further comprising:

forming a conductive control gate over and insulated from the floating gate;

forming a conductive erase gate laterally to one side of, and insulated from, the floating gate, wherein the erase gate is disposed at least partially over and insulated from the first region; and

the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.

10. The method of claim 6, wherein the stressor region is disposed underneath a surface of the substrate such that a surface portion of the substrate over the stressor region is a strained silicon layer.

11. The method of claim 6, wherein the forming of the stressor region of embedded silicon carbide in the substrate comprises:

selectively etching semiconductor material from a surface of the substrate to form a recess region in the substrate;

growing silicon carbide in the recess region; and

depositing semiconductor material over the silicon carbide.