MOSFET DEVICE AND FABRICATION

• US 20140091386A1
• Filed: 09/23/2013
• Published: 04/03/2014
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John, Lee, Il Kwan, Chang, Hong, Li, Wenjun, Bhalla, Anup, Yilmaz, Hamza
• Granted Patent: US 9,793,393 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region.

Claims

1. A semiconductor device, comprising:

a substrate;

an active gate trench in the substrate;

a source polysilicon pickup trench in the substrate;

a polysilicon electrode disposed in the source polysilicon pickup trench; and

a body region in the substrate;

wherein;

a top surface of the polysilicon electrode is below a bottom of the body region.

2. The semiconductor device of claim 1, further comprising a contact hole filled with a metal conductor extending from the polysilicon electrode to a source metal layer deposited on a top surface of the semiconductor device.

3. The semiconductor device of claim 2, wherein the contact hole is narrower in width than the polysilicon electrode.

4. The semiconductor device of claim 1, wherein the source polysilicon pickup trench is deeper than the active gate trench.

5. The semiconductor device of claim 1, wherein the source polysilicon pickup trench is narrower than the active gate trench.

6. A method of fabricating a semiconductor device, comprising:

forming an active gate trench and a source polysilicon pickup trench in a substrate;

forming an active gate electrode in the active gate trench and a polysilicon electrode in the source silicon pickup trench; and

implanting a body region;

wherein

the polysilicon electrode has a top surface that is below a bottom of the body region.

7. The method of claim 6, further comprising:

forming a contact hole above the a polysilicon electrode;

filling the contact hole with a metal conductor;

depositing a source metal layer on a top surface of the semiconductor device;

the metal conductor extending from the polysilicon electrode to a source metal layer deposited on top surface of semiconductor device.

8. The method of claim 7, wherein the contact hole is formed to be narrower in width than the polysilicon electrode.

9. The method of claim 6, wherein the source polysilicon pickup trench is formed to be deeper than the active gate trench.

10. The method of claim 6, wherein the source polysilicon pickup trench is formed to be narrower than the active gate trench.