SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

• US 20140091393A1
• Filed: 12/06/2013
• Published: 04/03/2014
• Est. Priority Date: 06/10/2011
• Status: Abandoned Application

• Current Assignee: National Institute of Advanced Industrial Science and Technology (Government of Japan), Sumitomo Chemical Company Limited, University of Tokyo
• Original Assignee: National Institute of Advanced Industrial Science and Technology (Government of Japan), Sumitomo Chemical Company Limited, University of Tokyo
• Inventors: HATA, Masahiko, YAMADA, Hisashi, YOKOYAMA, Masafumi, TAKENAKA, Mitsuru, TAKAGI, Shinichi, YASUDA, Tetsuji, Kim, SangHyeon
• Application Number:
  US14/099,427
• Publication Number:
  US 20140091393A1
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

There is provided a semiconductor device including: a first source and a first drain of a first-channel-type MISFET formed on a first semiconductor crystal layer, which are made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor crystal layer, a nickel atom, and a cobalt atom; and a second source and a second drain of a second-channel-type MISFET formed on a second semiconductor crystal layer, which are made of a compound having an atom constituting the second semiconductor crystal layer and a nickel atom, a compound having an atom constituting the second semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the second semiconductor crystal layer, a nickel atom, and a cobalt atom.

Claims

1. A semiconductor device comprising:

a base wafer;

a first semiconductor crystal layer positioned above the base wafer;

a second semiconductor crystal layer positioned above a partial area of the first semiconductor crystal layer;

a first MISFET having a channel formed in a part of an area of the first semiconductor crystal layer above which the second semiconductor crystal layer does not exist and having a first source and a first drain; and

a second MISFET having a channel formed in a part of the second semiconductor crystal layer and having a second source and a second drain, wherein

the first MISFET is a first-cannel-type MISFET and the second MISFET is a second-channel-type MISFET, the second-channel-type being different from the first-channel-type,

the first source and the first drain are made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor crystal layer, a nickel atom, and a cobalt atom, and

the second source and the second drain are made of a compound having an atom constituting the second semiconductor crystal layer and a nickel atom, a compound having an atom constituting the second semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the second semiconductor crystal layer, a nickel atom, and a cobalt atom.

2. The semiconductor device according to claim 1, further comprising:

a first separation layer that is positioned between the base wafer and the first semiconductor crystal layer, and electrically separates the base wafer from the first semiconductor crystal layer, and

a second separation layer that is positioned between the first semiconductor crystal layer and the second semiconductor crystal layer, and electrically separates the first semiconductor crystal layer from the second semiconductor crystal layer.

3. The semiconductor device according to claim 1, further comprising:

a second separation layer that is positioned between the first semiconductor crystal layer and the second semiconductor crystal layer, and electrically separates the first semiconductor crystal layer from the second semiconductor crystal layer, wherein

the base wafer is in contact with the first semiconductor crystal layer via a bonding plane,

impurity atoms exhibiting a p-type or n-type conductivity type are contained in an area of the base wafer in the vicinity of the bonding plane, and

impurity atoms exhibiting a conductivity type different from the conductivity type of impurity atoms contained in the base wafer are contained in an area of the first semiconductor crystal layer in the vicinity of the bonding plane.

4. The semiconductor device according to claim 2, wherein

the base wafer is in contact with the first separation layer,

an area of the base wafer that is in contact with the first separation layer is conductive, and

a voltage applied to the area of the base wafer that is in contact with the first separation layer functions as a back gate voltage with respect to the first MISFET.

5. The semiconductor device according to claim 2, wherein

the first semiconductor crystal layer is in contact with the second separation layer,

an area of the first semiconductor crystal layer that is in contact with the second separation layer is conductive, and

a voltage applied to the area of the first semiconductor crystal layer that is in contact with the second separation layer functions as a back gate voltage with respect to the second MISFET.

6. The semiconductor device according to claim 1, wherein

the first semiconductor crystal layer is made of a Group IV semiconductor crystal, and the first MISFET is a P-cannel-type MISFET, and

the second semiconductor crystal layer is made of a Group III-V compound semiconductor crystal, and the second MISFET is an N-channel-type MISFET.

7. The semiconductor device according to claim 1, wherein

the first semiconductor crystal layer is made of a Group III-V compound semiconductor crystal, and the first MISFET is an N-channel-type MISFET, and

the second semiconductor crystal layer is made of a Group IV semiconductor crystal, and the second MISFET is a P-channel-type MISFET.

8. A semiconductor wafer used for the semiconductor device according to claim 1, the semiconductor wafer comprising:

the base wafer, the first semiconductor crystal layer, and the second semiconductor crystal layer, wherein

the first semiconductor crystal layer is positioned above the base wafer, and

the second semiconductor crystal layer is positioned above a part or all of the first semiconductor crystal layer.

9. The semiconductor wafer according to claim 8, further comprising:

a first separation layer that is positioned between the base wafer and the first semiconductor crystal layer, and electrically separates the base wafer from the first semiconductor crystal layer, and

a second separation layer that is positioned between the first semiconductor crystal layer and the second semiconductor crystal layer, and electrically separates the first semiconductor crystal layer from the second semiconductor crystal layer.

10. The semiconductor wafer according to claim 9, wherein

the first separation layer is made of an amorphous insulator.

11. The semiconductor wafer according to claim 9, wherein

the first separation layer is made of a semiconductor crystal having a wider band gap than a bend gap of a semiconductor crystal constituting the first semiconductor crystal layer.

12. The semiconductor wafer according to claim 8, further comprising:

a second separation layer that is positioned between the first semiconductor crystal layer and the second semiconductor crystal layer, and electrically separates the first semiconductor crystal layer from the second semiconductor crystal layer, wherein

the base wafer is in contact with the first semiconductor crystal layer via a bonding plane,

impurity atoms exhibiting a p-type or n-type conductivity type are contained in an area of the base wafer in the vicinity of the bonding plane, and

impurity atoms exhibiting a conductivity type different from the conductivity type of impurity atoms contained in the base wafer are contained in an area of the first semiconductor crystal layer in the vicinity of the bonding plane.

13. The semiconductor wafer according to claim 9, wherein

the second separation layer is made of an amorphous insulator.

14. The semiconductor wafer according to claim 9, wherein

the second separation layer is made of a semiconductor crystal having a wider band gap than a band gap of a semiconductor crystal constituting the second semiconductor crystal layer.

15. The semiconductor wafer according to claim 8, comprising:

a plurality of the second semiconductor crystal layers, wherein

each of the plurality of second semiconductor crystal layers is arranged regularly within a plane parallel to an upper plane of the base wafer.

16. A method for producing the semiconductor wafer according to claim 8, the method comprising:

first semiconductor crystal layer forming of forming the first semiconductor crystal layer above the base wafer; and

second semiconductor crystal layer forming of forming the second semiconductor crystal layer above a partial area of the first semiconductor crystal layer, wherein

the second semiconductor crystal layer forming comprises;

epitaxial growth of forming the second semiconductor crystal layer on a semiconductor crystal layer forming wafer by epitaxial growth;

forming, on the first semiconductor crystal layer, on the second semiconductor crystal layer, or on both of the first semiconductor crystal layer and the second semiconductor crystal layer, a second separation layer that electrically separates the first semiconductor crystal layer from the second semiconductor crystal layer; and

bonding the base wafer including the first semiconductor crystal layer to the semiconductor crystal layer forming wafer so that the second separation layer positioned on the first semiconductor crystal layer will be bonded to the second semiconductor crystal layer, that the second separation layer positioned on the second semiconductor crystal layer will be bonded to the first semiconductor crystal layer, or that the second separation layer positioned on the first semiconductor crystal layer will be bonded to the second separation layer positioned on the second semiconductor crystal layer.

17. The method according to claim 16, for producing the semiconductor wafer, wherein

the first semiconductor crystal layer forming comprises:

epitaxial growth of forming the first semiconductor crystal layer on a semiconductor crystal layer forming wafer by epitaxial growth;

forming, on the base wafer, on the first semiconductor crystal layer, or an both of the base wafer and the first semiconductor crystal layer, a first separation layer that electrically separates the base wafer from the first semiconductor crystal layer; and

bonding the base wafer to the semiconductor crystal layer forming wafer so that the first separation layer positioned on the base wafer will be bonded to the first semiconductor crystal layer, that the first separation layer positioned on the first semiconductor crystal layer will be bonded to the base wafer, or that the first separation layer positioned on the base wafer will be bonded to the first separation layer positioned on the first semiconductor crystal layer.

18. The method according to claim 16, for producing the semiconductor wafer, wherein

the first semiconductor crystal layer is made of SiGe, and the second semiconductor crystal layer is made of a Group III-V compound semiconductor crystal,

the method comprises, prior to the first semiconductor crystal layer forming, forming a first separation layer made of an insulator on the base wafer, and

the first semiconductor crystal layer forming comprises:

forming a SiGe layer, which serves as a starting material of the first semiconductor crystal layer, on the first separation layer; and

enhancing the concentration of Ge atom in the SiGe layer by beating the SiGe layer in an oxidizing atmosphere to oxidize a surface.

19. The method according to claim 16, for producing the semiconductor wafer, wherein

the first semiconductor crystal layer is made of a Group IV semiconductor crystal, and the second semiconductor crystal layer is made of a Group III-V compound semiconductor crystal, the method comprising:

forming a first separation layer made of an insulator on a surface of a semiconductor layer material wafer made of a Group IV semiconductor crystal;

injecting, via the first separation layer, cations to a predetermined separation depth of the semiconductor layer material wafer;

bonding the semiconductor layer material wafer to the base wafer, so that a surface of the first separation layer will be bonded to a surface of the base wafer;

degenerating the Group IV semiconductor crystal positioned at the predetermined separation depth by heating the semiconductor layer material wafer and the base wafer, and reacting the cations having been injected to the predetermined separation depth and Group IV atoms constituting the semiconductor layer material wafer; and

separating the semiconductor layer material wafer from the base wafer, thereby detaching, from the semiconductor layer material wafer, a portion of the Group IV semiconductor crystal positioned between the base wafer and the degenerated portion of the Group IV semiconductor crystal.

20. The method according to claim 16, for producing the semiconductor wafer, comprising, prior to the first semiconductor crystal layer forming, forming, on the base wafer, a first separation layer made of a semiconductor crystal having a wider band gap than a bend gap of a semiconductor crystal constituting the first semiconductor crystal layer by epitaxial growth, wherein

the first semiconductor crystal layer forming is forming the first semiconductor crystal layer on the first separation layer by epitaxial growth.

21. The method according to claim 16, for producing the semiconductor wafer, wherein

the first semiconductor crystal layer forming is forming the first semiconductor crystal layer on the base wafer by epitaxial growth.

22. The method according to claim 21, for producing the semiconductor wafer, wherein

impurity atoms exhibiting a p-type or n-type conductivity type are contained in the vicinity of a surface of the base wafer, and

in the forming of the first semiconductor crystal layer by epitaxial growth, the first semiconductor crystal layer is doped with impurity atoms exhibiting a conductivity type different from a conductivity type of impurity atoms contained in the base wafer.

23. The method according to claim 14, for producing the semiconductor wafer, comprising:

second semiconductor crystal layer forming of forming the second semiconductor crystal layer on a semiconductor crystal layer forming wafer by epitaxial growth;

second separation layer forming of forming, on the second semiconductor crystal layer, a second separation layer made of a semiconductor crystal having a wider band gap than a bend gap of a semiconductor crystal constituting the second semiconductor crystal layer by epitaxial growth;

first semiconductor crystal layer forming of forming the first semiconductor crystal layer on the second separation layer by epitaxial growth;

forming, on the base wafer, on the first semiconductor crystal layer, or on both of the base wafer and the first semiconductor crystal layer, a first separation layer that electrically separates the base wafer from the first semiconductor crystal layer; and

bonding the base wafer to the semiconductor crystal layer forming wafer so that the first separation layer positioned on the base wafer will be bonded to the first semiconductor crystal layer, that the first separation layer positioned on the first semiconductor crystal layer will be bonded to the base wafer, or that the first separation layer positioned on the base wafer will be bonded to the first separation layer positioned on the first semiconductor crystal layer.

24. The method according to claim 16, for producing the semiconductor wafer, further comprising:

prior to forming a semiconductor crystal layer on the semiconductor crystal layer forming wafer, forming a crystalline sacrificial layer on a surface of the semiconductor crystal layer forming wafer by epitaxial growth; and

separating the semiconductor crystal layer forming wafer from the semiconductor crystal layer having been formed by epitaxial growth on the semiconductor crystal layer forming wafer, by removing the crystalline sacrificial layer, after bonding the base wafer to the semiconductor crystal layer forming wafer.

25. The method according to claim 16, far producing the semiconductor wafer, comprising:

any one of patterning the second semiconductor crystal layers in a regular alignment after having formed the second semiconductor crystal layers by epitaxial growth, or forming the second semiconductor crystal layers in a regular alignment by selective epitaxial growth.

26. A method for producing a semiconductor device, the method comprising:

producing a semiconductor wafer comprising the first semiconductor crystal layer and the second semiconductor crystal layer by using the method according to claim 16 for producing the semiconductor wafer;

forming a gate electrode above each of the first semiconductor crystal layer and the second semiconductor crystal layer, with a gate insulating layer therebetween;

forming a metal film selected from the group consisting of a nickel film, a cobalt film, and a nickel/cobalt alloy film, on a source electrode forming region of the first semiconductor crystal layer, on a drain electrode forming region of the first semiconductor crystal layer, on a source electrode forming region of the second semiconductor crystal layer, and on a drain electrode forming region of the second semiconductor crystal layer;

heating the metal film, thereby forming, in the first semiconductor crystal layer, a first source and a first drain made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor crystal layer, a nickel atom, and a cobalt atom, and forming, in the second semiconductor crystal layer, a second source and a second drain made of a compound having an atom constituting the second semiconductor crystal layer and a nickel atom, a compound having an atom constituting the second semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the second semiconductor crystal layer, a nickel atom, and a cobalt atom; and

removing a non-reacted portion of the metal film.