SHIFT REGISTER AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME

• US 20140091997A1
• Filed: 12/27/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Han, HwaDong, Park, ChongHun, Jeong, IIGi, Park, JoonMin
• Granted Patent: US 9,190,169 B2
• Time in Patent Office: Days
• US Class Current: 345/92
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present disclosure relates to a shift register, and more particularly, a shift register having a sensing circuit for quantitatively measuring a threshold voltage shifted level of a thin film transistor, which is deteriorated due to a continuously applied direct-current (DC) voltage, in a shift register having thin film transistors using oxide silicon as an active layer.

The present disclosure may provide a shift register capable of overcoming an erroneous operation caused due to lowering of device characteristics, by further connecting a sensing transistor to thin film transistors configuring the shift register formed on a display panel to sense a level of threshold voltage shift, and driving the shift register by dividing one frame into odd and even periods according to the sensing result.

Claims

1. A shift register comprising:

transistors belonging to a first group for activating a Q node;

transistors belonging to a second group for discharging odd and even QB nodes; and

transistors belonging to a third group for activating the odd and even QB nodes and discharging the Q node,

wherein the shift register comprises a sensing circuit to sense a threshold voltage of at least one of the transistors belonging to the third group.

2. The shift register of claim 1, wherein the transistors of the first group comprise:

a first transistor connected between a power supply voltage end and the Q node to apply a power supply voltage to the Q node in response to a start signal or a preceding stage output signal; and

a sixth transistor connected between a clock signal end and an output signal end to output the clock signal as a gate output signal when the Q node is charged with a high level voltage.

3. The shift register of claim 2, wherein the transistors of the first group further comprise a 6N transistor connected between the clock signal end and a carry signal end to output the clock signal as a carry signal when the Q node is charged with a high level voltage.

4. The shift register of claim 1, wherein the transistors of the second group comprise:

a 4A_O transistor diode-connected, and connected between an odd power supply voltage end and a 4Q_O transistor, the 4A_O transistor turning a 4_O transistor when an odd power supply voltage of high level is applied;

a 4_O transistor connected between the odd power supply voltage end and the odd QB node, the 4_O transistor charging the odd QB node with a high level voltage when an odd power supply voltage of high level is applied from the 4_AO transistor;

a 4Q_O transistor connected between the 4A_O transistor and the ground voltage end, the 4Q_O transistor turning off the 4A_O transistor when the Q node is charged with a high level voltage;

a 4A_E transistor diode-connected, and connected between the even power supply voltage end and the 4Q_E transistor, the 4A_E transistor turning on the 4_E transistor when an even power supply voltage of high level is applied;

a 4_E transistor connected between the even power supply voltage end and the even QB node, the 4_E transistor charging the even QB node with a high level voltage when an even power supply voltage of high level is applied from the 4A_E transistor;

a 4Q_E transistor connected between the 4A_E transistor and the ground voltage end, the 4Q_E transistor turning off the 4A_E transistor when the Q node is charged with a high level voltage;

a 5Q_O transistor connected between the odd QB node and the ground voltage end, the 5Q_O transistor discharging the odd QB node when the Q node is charged with a high level voltage;

a 5_O transistor connected between the odd QB node and the ground voltage end, the 5_O transistor discharging the odd QB node when a start signal is applied;

a 5Q_E transistor connected between the even QB node and the ground voltage end, the 5Q_E transistor discharging the even QB node when the Q node is charged with a high level voltage; and

a 5_E transistor connected between the even-numbered QB node and the ground voltage end, the 5_E transistor discharging the odd QB node when the start signal is applied.

5. The shift register of claim 4, wherein the odd power supply voltage and the even power supply voltage are voltage signals compensated for based on a level of threshold voltage shift sensed by the sensing circuit.

6. The shift register of claim 1, wherein the transistors of the third group comprise:

a 3N transistor connected between the Q node and the ground voltage end, the 3N transistor discharging the Q node in response to the next signal applied from the succeeding stage;

a 3_O transistor connected between the Q node and the ground voltage end, the 3_O transistor discharging the Q node when the odd QB node transits into a high level;

a 3_E transistor connected between the Q node and the ground voltage end, the 3_E transistor discharging the Q node when the even QB node transits into a high level;

a 5Q_O transistor connected between the odd QB node and the ground voltage end, the 5Q_O transistor discharging the odd QB node when the Q node is charged with a high level voltage;

a 5_O transistor connected between the odd QB node and the ground voltage end, the 5_O transistor discharging the odd QB node when the start signal is applied;

a 5Q_E transistor connected between the even QB node and the ground voltage end, the 5Q_E transistor discharging the even QB node when the Q node is charged with a high level voltage;

a 5_E transistor connected between the even QB node and the ground voltage end, the 5_E transistor discharging the odd QB node when the start signal is applied;

a 7N_O transistor connected between a carry signal end and the ground voltage end, the 7N_O transistor stopping the output of a carry signal when the odd QB node is charged with a high level voltage;

a 7N_E transistor connected between the carry signal end and the ground voltage end, the 7N_E transistor stopping the output of the carry signal when the even QB node is charged with a high level voltage;

a 7_O transistor connected between the output signal end and the ground voltage end, the 7_O transistor outputting a gate output signal of low level when the odd QB node transits into a high level; and

a 7_E transistor connected between the output signal end and the ground voltage end, the 7_E transistor outputting a gate output signal of low level when the even QB node transits into a high level.

7. The shift register of claim 5, wherein the odd power supply voltage and the even power supply voltage are voltage signals compensated for based on a level of threshold voltage shift sensed by the sensing circuit.

8. The shift register of claim 1, wherein the sensing circuit comprises:

a first ST transistor connected between the odd QB node and one electrode of a target transistor, the first ST transistor allowing the target transistor to be diode-connected in response to a second sensing control signal;

a second ST transistor connected between one electrode of the target transistor and the ground voltage end, the second ST transistor electrically disconnecting the target transistor from the ground voltage end in response to a first sensing control signal;

a third ST transistor connected between the target transistor and the second ST transistor, the third ST transistor electrically connecting the target transistor to a constant current supply in response to the second sensing control signal; and

a fourth ST transistor connected between another electrode of the target transistor and the ground voltage end, the fourth ST transistor allowing a current flowing via the target transistor to be applied to the sensing circuit in response to the second sensing control signal.

9. The shift register of claim 8, wherein the target transistor is electrically connected to at least one of the transistors connected to the odd QB node and the even QB node.

10. A flat panel display device comprising:

a display panel having a plurality of gate and data lines intersecting with each other to define pixels on the intersecting point;

a gate driving unit mounted onto one side of the display panel, and including a shift register having a plurality of stages for outputting a gate output signal to the gate lines; and

a data driving unit disposed on one side of the display panel to output a data voltage to the data lines in response to the output signal,

wherein the shift register comprises;

transistors belonging to a first group for activating a Q node;

transistors belonging to a second group for discharging odd and even QB nodes; and

transistors belonging to a third group for activating the odd and even QB nodes and discharging the Q node,

wherein at least one of the transistors belonging to the third group is connected to a sensing circuit to sense a level of threshold voltage shift.

11. The device of claim 10, further comprising a compensation sensing unit to supply first and second sensing control signals, corresponding to a gate high-level voltage and a gate low-level voltage, to the sensing circuit, and supply compensated odd power supply voltage and even power supply voltage to the shift register by calculating the level of the threshold voltage shift sensed by the sensing circuit.