Data storage in memory array with less than half of cells in any row and column in low-resistance states

• US 20140092667A1
• Filed: 09/28/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ordentlich, Erik, Roth, Ron M.
• Granted Patent: US 8,861,256 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method of storing data in a memory array with less than half of memory elements in any row and column in a low-resistance state. The data are arranged in a first portion of an encoding array. High-resistance values are entered in a second portion. A codeword is selected from a covering code for each row in which too many entries have low-resistance values. The selected codeword is used to reduce the number of low-resistance values in that row. A codeword is selected for each column in which too many entries have low-resistance values and the codeword is used to reduce the number of such values in that column. The process is repeated until no row and no column has too many low-resistance values. The array entries are stored in corresponding memory elements.

Claims

1. A method of storing binary data in a memory array with less than half of memory elements in any row and column of the array in a low-resistance state, the method comprising:

arranging the binary data in a first portion of an encoding array, the encoding array having as many rows and columns as the memory array;

entering high-resistance values in a second portion of the encoding array;

selecting, from a covering code with a radius equal to a predetermined number that is less than half the number of rows in the encoding array, a codeword for each row in which more entries than the predetermined number are low-resistance values;

using the codeword for each such row to reduce the number of low-resistance values in that row;

selecting from the covering code a codeword for each column in which more entries than the predetermined number are low-resistance values;

using the codeword for each such column to reduce the number of low-resistance values in that column;

if any row or column still has too many low-resistance values, repealing the preceding steps of selecting and using codewords until no row and no column has more low-resistance values than the predetermined number; and

storing the entries from the encoding array in corresponding memory elements of the memory array.

2. The method of claim 1 wherein the covering code has a dimension equal to the number of rows in the second portion of the encoding array.

3. The method of claim 1 wherein the codeword for each row and column is within a Hamming distance from that row or column, the Hamming distance being equal to the covering radius.

4. The method of claim 3 wherein reducing the number of low-resistance values in a row comprises replacing the row with a componentwise modulo-2 sum of the row and the codeword for that row.

5. The method of claim 3 wherein reducing the number of low-resistance values in a column comprises replacing the column with a componentwise modulo-2 sum of the column and the codeword for that column.

6. The method of claim 5 and further comprising retrieving the binary data from the memory array by reading entries from the memory elements into a decoding array, decoding the entries using information in the appended rows and columns, and arranging the decoded entries into a data string.

7. The method of claim 4 wherein:

the encoding array is a square array; and

arranging the data in the first portion of the encoding array comprises entering high-resistance values in diagonal positions of that portion and entering the data into other positions.

8. The method of claim 7 wherein reducing the number of low-resistance values in a column comprises applying an antipodal matching to the column.

9. The method of claim 8 and further comprising replacing entries in diagonal positions of the encoding array with coding information.

10. The method of claim 9 and further comprising retrieving the binary data from the memory elements by reading entries from the memory elements into a decoding array, decoding the entries using information in diagonals of the decoding array, and arranging the decoded entries into a data string.

11. The method of claim 10 wherein decoding the entries comprises applying an inverse antipodal matching to rows of the decoding array.

12. A memory system that stores binary data with less than one-half of storage cells in any row and column of a memory array in low resistance states at the same time, the system comprising:

a plurality of row and column conductors;

a plurality of storage cells capable of being placed into any of two or more resistance states, each cell connected between a different combination of row and column conductors to define a memory array; and

a memory controller to;

receive binary data for storage;

arrange the data in a first portion of an encoding array, the encoding array having as many rows and columns as the memory array;

enter high-resistance values in a second portion of the encoding array;

select a codeword, from a covering code having a covering radius equal to a predetermined number that is less than one-half the number of rows of the encoder array, for each row of the encoder array having more entries than the predetermined number corresponding with low resistance states, and change the entries in that row according to the selected codeword;

select a codeword from the covering code for each column of the encoder array having more entries than the predetermined number corresponding with low resistance states, and change the entries in that column according to the selected codeword;

if any row or column still has too many low-resistance values, repeating the preceding steps of selecting codewords and changing entries until no row and no column has more low-resistance values than the predetermined number; and

apply signals to the row and column conductors to write entries from the encoder array into the cells.

13. The system of claim 12 wherein the storage cells comprise at least one of memristors and chalcogenide phase change memory cells.

14. The system of claim 12 wherein entries in a row or column are changed by replacing the entire row or column with a componentwise modulo-2 sum of the row or column and the codeword for the row or column and repeating until no more entries than the predetermined number in that row or column correspond with low resistance states.

15. The system of claim 12 wherein entries in a row are changed by replacing the entire row with a componentwise modulo-2 sum of the row and the codeword for the row, and entries in a column are changed by applying an antipodal matching to a subsequence of the column.