Fully-Digital BIST for RF Receivers

• US 20140092946A1
• Filed: 09/28/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Inventors: Kuenen, Jeroen, Dhayni, Achraf
• Granted Patent: US 8,879,611 B2
• Time in Patent Office: Days
• US Class Current: 375/224
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 17/20 of receivers
• CPC Class Codes: H04B 17/29 Performance testing

Abstract

A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.

Claims

1. A method of testing a receiver to measure an intermodulation tone at using a built-in self-test system, the method comprising:

generating a test signal using a stimulus generator, the test signal comprising first and second tones at respective first and second frequencies, wherein the first and second frequencies are spaced by an offset frequency, and wherein the first frequency comprises a non-integer multiple of the offset frequency;

applying the test signal to a downconverter of the receiver to downconvert the test signal to generate an In-phase component and a Quadrature component; and

demodulating, in a demodulator of the receiver, the In-phase and Quadrature components based on a reference frequency to measure an amplitude of the intermodulation tone,

wherein the stimulus generator, the downconverter, and the demodulator are disposed on a common receiver chip.

2. The method of claim 1 further comprising calculating a linearity parameter for the receiver based on the amplitude of the intermodulation tone.

3. The method of claim 2 wherein the intermodulation tone comprises a second order intermodulation tone, and wherein the linearity parameter comprises a second order intercept point.

4. The method of claim 2 wherein the intermodulation tone comprises a third order intermodulation tone, and wherein the linearity parameter comprises a third order intercept point.

5. The method of claim 1 wherein generating the test signal comprises:

generating a first signal at the first frequency based on an oscillator output signal at an oscillator frequency;

dividing the oscillator output signal by a first divisor to generate an offset signal at the offset frequency; and

generating the test signal by switching the first signal on and off responsive to the offset signal.

6. The method of claim 5 wherein generating the first signal at the first frequency comprises:

dividing the oscillator output signal by a second value to generate a third signal at a third frequency; and

generating the first signal based on the third signal.

7. The method of claim 5 further comprising determining the non-integer multiple and the first divisor based on a desired relationship between the first frequency and the oscillator frequency.

8. The method of claim 7 wherein determining the non-integer multiple and the first divisor comprises determining the non-integer multiple and the first divisor satisfying

9. A built-in receiver self-test system for measuring an intermodulation tone, the system comprising:

a stimulus generator configured to generate a test signal, the test signal comprising first and second tones at respective first and second frequencies, wherein the first and second frequencies are spaced by an offset frequency, and wherein the first frequency comprises a non-integer multiple of the offset frequency;

a downconverter operatively connected to the stimulus generator and configured to downconvert the test signal to generate an In-phase component and a Quadrature component; and

a demodulator operatively connected to the downconverter and configured to measure an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency,

wherein the stimulus generator, the downconverter, and the demodulator are disposed on a common receiver chip.

10. The system of claim 9 further comprising a processor configured to calculate a linearity parameter for the receiver based on the amplitude of the intermodulation tone.

11. The system of claim 10 wherein the intermodulation tone comprises a second order intermodulation tone, and wherein the linearity parameter comprises a second order intercept point.

12. The system of claim 10 wherein the intermodulation tone comprises a third order intermodulation tone, and wherein the linearity parameter comprises a third order intercept point.

13. The system of claim 9 wherein the on-chip stimulus generator comprises:

a first signal generator configured to generate a first signal at the first frequency based on an oscillator output signal at an oscillator frequency;

a first divider to divide the oscillator output signal by a first value to generate an offset signal at the offset frequency; and

a logic gate configured to generate the test signal by switching the first signal on and off responsive to the offset signal.

14. The system of claim 13 wherein the first signal generator comprises:

a second divider to divide the oscillator output signal by a second value to generate a third signal at a third frequency; and

a phase-locked loop configured to generate the first signal based on the third signal.

15. The system of claim 13 further comprising a processor configured to determine the non-integer multiple and the first divisor based on a desired relationship between the first frequency and the oscillator frequency.

16. The system of claim 15 wherein the processor determines the non-integer multiple and the first divisor to satisfy

17. A method of generating a test signal for a built-in receiver self-test system used to measure an intermodulation tone, the method comprising:

generating a first signal at a first frequency based on an oscillator output signal at an oscillator frequency, said first frequency being less than said oscillator frequency;

dividing the oscillator output signal by a first divisor to generate an offset signal at an offset frequency; and

generating the test signal by switching the first signal on and off responsive to the offset signal, the test signal comprising a first tone at the first frequency and a second tone at a second frequency separated from the first frequency by the offset frequency, wherein the first frequency comprises a non-integer multiple of the offset frequency.

18. The method of claim 17 wherein the non-integer multiple comprises an integer value offset by 0.5.

19. The method of claim 17 further comprising determining the non-integer multiple and the first divisor based on a desired relationship between the first frequency and the oscillator frequency.

20. The method of claim 19 wherein determining the non-integer multiple and the first divisor comprises determining the non-integer multiple and the first divisor satisfying

21. The method of claim 17 wherein generating the first signal at the first frequency comprises:

dividing the oscillator output signal by a second value to generate a third signal at a third frequency; and

generating the first signal based on the third signal.

22. The method of claim 17 wherein the intermodulation tone comprises a second order intermodulation tone.

23. The method of claim 17 wherein the intermodulation tone comprises a third order intermodulation tone.

24. A test signal generator for a built-in receiver self-test system used to measure an intermodulation tone, the test signal generator comprising:

a first signal generator configured to generate a first signal at a first frequency based on an oscillator output signal at an oscillator frequency;

a first divider to divide the oscillator output signal by a first divisor to generate an offset signal at an offset frequency; and

a logic gate operatively connected to an output of the first signal generator and the first divider, the logic gate configured to switch the first signal on and off responsive to the offset signal to generate the test signal, the test signal comprising a first tone at the first frequency and a second tone at a second frequency separated from the first frequency by the offset frequency, wherein the first frequency comprises a non-integer multiple of the offset frequency.

25. The test signal generator of claim 24 wherein the non-integer multiple comprises an integer value offset by 0.5.

26. The test signal generator of claim 24 further comprising a processor configured to determine the non-integer multiple and the first divisor based on a desired relationship between the first frequency and the oscillator frequency.

27. The test signal generator of claim 26 wherein the processor determines the non-integer multiple and the first divisor to satisfy

28. The test signal generator of claim 24 wherein the first signal generator comprises:

a second divider to divide the oscillator output signal by a second divisor to generate a third signal at a third frequency; and

a phase-locked loop configured to generate the first signal based on the third signal.

29. The test signal generator of claim 24 wherein the intermodulation tone comprises a second order intermodulation tone.

30. The test signal generator of claim 24 wherein the intermodulation tone comprises a third order intermodulation tone.

31. The test signal generator of claim 24 wherein the logic gate comprises an AND gate.

32. The test signal generator of claim 24 wherein the first signal generator, the first divider, and the logic gate are disposed on a receiver chip.