DISTRIBUTED POLYPHASE FILTER

• US 20140093009A1
• Filed: 09/28/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Song, Hongjiang
• Granted Patent: US 9,252,743 B2
• Time in Patent Office: Days
• US Class Current: 375/295
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 2007/0192 Complex filters
• CPC Class Codes: H03H 2011/0494 Complex filters
• CPC Class Codes: H03H 7/185 comprising distributed impedance elements together with lumped impedance elements
• CPC Class Codes: H03H 7/21 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase

Abstract

In one embodiment, an apparatus includes a clock generator to generate differential clock signals. The apparatus also includes a distributed polyphase filter to obtain phase-corrected multi-phase clock signals based on the differential clock signals.

Claims

1. An apparatus comprising:

a clock generator to generate differential clock signals; and

a distributed polyphase filter to obtain phase-corrected multi-phase clock signals based on the differential clock signals.

2. The apparatus of claim 1, further comprising transmit logic to generate at least one data signal based on the phase-corrected multi-phase clock signals.

3. The apparatus of claim 1, further comprising receiver logic to recover at least one data signal based on the phase-corrected multi-phase clock signals.

4. The apparatus of claim 1, wherein the distributed polyphase filter is to reduce phase distortion in the differential clock signals.

5. The apparatus of claim 1, wherein the distributed polyphase filter comprises at least four inverters.

6. The apparatus of claim 5, wherein the at least four inverters comprise a first inverter, wherein an input of the first inverter is coupled to a positive signal of a first pair of differential clock signals, and wherein an output of the first inverter is coupled to a positive signal of a second pair of differential clock signals.

7. The apparatus of claim 5, wherein the at least four inverters comprise a second inverter, wherein an input of the second inverter is coupled to a negative signal of a first pair of differential clock signals, and wherein an output of the second inverter is coupled to a negative signal of a second pair of differential clock signals.

8. The apparatus of claim 5, wherein the at least four inverters comprise a third inverter, wherein an input of the third inverter is coupled to a positive signal of a second pair of differential clock signals, and wherein an output of the third inverter is coupled to a negative signal of a first pair of differential clock signals.

9. The apparatus of claim 5, wherein the at least four inverters comprise a fourth inverter, wherein an input of the fourth inverter is coupled to a negative signal of a second pair of differential clock signals, and wherein an output of the fourth inverter is coupled to a positive signal of a first pair of differential clock signals.

10. The apparatus of claim 1, wherein the phase-corrected multi-phase clock signals comprise a first pair of differential clock signals corresponding to a clock signal for an in-phase component.

11. The apparatus of claim 1, wherein the phase-corrected multi-phase clock signals comprise a second pair of differential clock corresponding to a clock signal for a quadrature component.

12. A system comprising:

a system on a chip comprising at least one core having at least one execution unit and transmit logic, the transmit logic comprising;

a clock generator to generate one or more clock signals;

a distributed polyphase filter to obtain multi-phase clock signals by phase-correcting the one or more clock signals; and

a wireless device coupled to the system on the chip via an interconnect, the interconnect used to communicate at least one data signal between the wireless device and the transmit logic of the system on the chip.

13. The system of claim 12, further comprising a distribution network to distribute the multi-phase clock signals.

14. The system of claim 12, the transmit logic to generate the at least one data signal based on the multi-phase clock signals.

15. The system of claim 12, wherein the distributed polyphase filter comprises at least four inverters.

16. The system of claim 12, wherein the distributed polyphase filter comprises at least two current mode logic (CML) differential buffers.

17. The system of claim 12, wherein the distributed polyphase filter comprises at least two pseudo-differential differential buffers.

18. A method comprising:

generating a plurality of differential clock signals;

correcting, using a distributed polyphase filter, the differential clock signals to obtain a plurality of phase-corrected multi-phase clock signals; and

recovering a plurality of differential data signals using the plurality of phase-corrected multi-phase clock signals.

19. The method of claim 18, wherein the phase-corrected multi-phase clock signals comprise four differential clock signals.

20. The method of claim 18, wherein the distributed polyphase filter comprises at least four inverters.

21. The method of claim 18, wherein the distributed polyphase filter comprises at least two current mode logic (CML) differential buffers.

22. The method of claim 18, wherein the distributed polyphase filter comprises at least two pseudo-differential differential buffers.