METHODS, SYSTEMS AND APPARATUS TO CACHE CODE IN NON-VOLATILE MEMORY

• US 20140095778A1
• Filed: 09/28/2012
• Published: 04/03/2014
• Est. Priority Date: 09/28/2012
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chung, Jaewoong, Wang, Cheng, Wu, Youfeng
• Application Number:
  US13/630,651
• Publication Number:
  US 20140095778A1
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/4552 Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM

Abstract

Methods and apparatus are disclosed to cache code in non-volatile memory. A disclosed example method includes identifying an instance of a code request for first code, identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache, and when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.

Claims

1. A method to cache code, comprising:

identifying an instance of a code request for first code;

identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache; and

when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.

2. A method as defined in claim 1, further comprising determining whether an aggregate threshold corresponding to the first condition and a second condition is met when the first condition is not met.

3. A method as defined in claim 1, wherein the code request is initiated by a processor.

4. A method as defined in claim 1, wherein the code request is initiated by at least one of a compiler or a binary translator.

5. A method as defined in claim 1, wherein the NV RAM cache permits byte level access.

6. A method as defined in claim 1, wherein the first condition comprises an access frequency count exceeds a threshold.

7. A method as defined in claim 6, further comprising setting the threshold for the access frequency count based on an access frequency count value of second code.

8. A method as defined in claim 6, further comprising setting the threshold for the access frequency count based on an access frequency count value associated with a plurality of other code.

9. A method as defined in claim 1, wherein the first condition comprises at least one of an access frequency count, a translation time, a code size, or a cache access latency.

10. A method as defined in claim 1, further comprising compiling the first code with a binary translator before adding the first code to the NV RAM cache.

11. A method as defined in claim 1, further comprising tracking a number of processor requests for the first code.

12. A method as defined in claim 11, further comprising adding the first code to the NV RAM cache based on the number of requests for the first code.

13. A method as defined in claim 1, further comprising tracking a number of write operations to the NV RAM cache.

14. A method as defined in claim 13, further comprising generating an alert when the number of write operations to the NV RAM cache exceeds a threshold write value associated with a lifetime maximum number of writes.

15. A method as defined in claim 1, further comprising overriding a storage attempt to the NV RAM cache when the first code is absent from a first level cache.

16. A method as defined in claim 15, wherein the storage attempt to the NV RAM cache is associated with a least recently used storage policy.

17. An apparatus to store dynamically compiled code, comprising:

a first level cache to store the compiled code;

a second level non-volatile (NV) random access memory (RAM) cache to store the compiled code; and

a cache interface to permit storage of the compiled code in the NV RAM if the compiled code is accessed at a greater than a threshold frequency, and to block storage of the compiled code on the NV RAM if the threshold frequency is not met.

18. An apparatus as defined in claim 17, wherein the first level cache comprises dynamic random access memory.

19. An apparatus as defined in claim 17, further comprising a profile manager to compare an expected lifetime write count value associated with the NV RAM cache with a current number of write count instances of the NV RAM cache.

20. An apparatus as defined in claim 19, further comprising a condition threshold engine to set a threshold associated with a second condition to reduce a frequency of write count instances to the NV RAM cache.

21. A tangible machine readable storage medium comprising instructions that, when executed, cause a machine to, at least:

identify an instance of a code request for first code;

identify whether the first code is stored on non-volatile (NV) random access memory (RAM) cache; and

when the first code is absent from the NV RAM cache, add the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.

22. A machine readable storage medium as defined in claim 21, wherein the instructions, when executed, cause a machine to determine whether an aggregate threshold corresponding to the first condition and a second condition is met when the first condition is not met.

23. A machine readable storage medium as defined in claim 21, wherein the instructions, when executed, cause a machine to permit byte level access via the NV RAM cache.

24. A machine readable storage medium as defined in claim 21, wherein the instructions, when executed, cause a machine to identify when the first condition exceeds a threshold count access frequency.

25. A machine readable storage medium as defined in claim 24, wherein the instructions, when executed, cause a machine to set the threshold for the access frequency count based on an access frequency count value of second code.

26. A machine readable storage medium as defined in claim 24, wherein the instructions, when executed, cause a machine to set the threshold for the access frequency count based on an access frequency count value associated with a plurality of other code.

27. A machine readable storage medium as defined in claim 21, wherein the instructions, when executed, cause a machine to track a number of processor requests for the first code.

28. A machine readable storage medium as defined in claim 27, wherein the instructions, when executed, cause a machine to add the first code to the NV RAM cache based on the number of requests for the first code.

29. A machine readable storage medium as defined in claim 21, wherein the instructions, when executed, cause a machine to track a number of write operations to the NV RAM cache.

30. A machine readable storage medium as defined in claim 29, wherein the instructions, when executed, cause a machine to generate an alert when the number of write operations to the NV RAM cache exceeds a threshold write value associated with a lifetime maximum number of writes.

31. A machine readable storage medium as defined in claim 21, wherein the instructions, when executed, cause a machine to override a storage attempt to the NV RAM cache when the first code is absent from a first level cache.