CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD

• US 20140095792A1
• Filed: 12/05/2013
• Published: 04/03/2014
• Est. Priority Date: 06/29/2011
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: HATAIDA, Makoto, ISHIZUKA, Takaharu, YAMAMOTO, TAKASHI, HOSOKAWA, Yuka
• Application Number:
  US14/097,306
• Publication Number:
  US 20140095792A1
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure

Abstract

A cache control device includes an entering unit, a first searching unit, a reading unit, a second searching unit, and a rewriting unit. The entering unit alternately enters, into a pipeline, a load request for reading a directory received from a processor and a store request for rewriting a directory received from the processor. When the first searching unit determines that the directory targeted by the load request is present in the first cache memory or the second cache memory, the reading unit reads the directory from the cache memory in which the directory is present. When the second searching unit determines that the directory targeted by the store request is present in the first cache memory, the rewriting unit rewrites the directory that is stored in the first cache memory.

Claims

1. A cache control device comprising:

an entering unit that alternately enters, into a pipeline, a load request for reading a directory that is received from a processor and a store request for rewriting a directory that is received from the processor;

a first searching unit that receives the load request that is entered by the entering unit, that searches a second cache memory and a first cache memory in which the speed of reading and writing data is higher than the speed of reading and writing data in the second cache memory, and that determines whether a directory targeted by the load request is present;

a reading unit that reads, when the first searching unit determines that the directory targeted by the load request is present in the first cache memory or the second cache memory, the directory from the cache memory in which the directory is present;

a second searching unit that receives the store request that is entered by the entering unit, that searches the first cache memory, and that determines whether a directory targeted by the store request is present; and

a rewriting unit that rewrites, when the second searching unit determines that the directory is present in the first cache memory, the directory in the first cache memory.

2. The cache control device according to claim 1, wherein

when the second searching unit determines that the directory targeted by the store request is not present in the first cache memory, the entering unit re-enters the store request as a load request into a pipeline, and

the first searching unit receives the load request that is re-entered by the entering unit, searches the second cache memory, and determines whether a directory targeted by the load request is present.

3. The cache control device according to claim 1, wherein, when the first searching unit determines that the directory is not present in the first cache memory nor the second cache memory, the reading unit reads a directory targeted by the load request from a main memory.

4. The cache control device according to claim 3, further comprising a storing unit that stores, in the first cache memory when the first searching unit or the second searching unit determines that the directory is not present in the first cache memory, the directory read by the reading unit.

5. The cache control device according to claim 4, wherein, when the second searching unit determines that the directory targeted by the store request is not present in the first cache memory, the entering unit re-enters the store request into a pipeline after the storing unit stores the directory in the first cache memory.

6. The cache control device according to claim 1, further comprising:

a determining unit that determines, when the first searching unit determines that the directory is not present in the first cache memory, whether a free entry is present in the first cache memory; and

a moving unit that selects, when the determining unit determines that the free entry is not present in the first cache memory, an entry from the first cache memory and that moves the selected entry to the second cache memory.

7. The cache control device according to claim 6, further comprising a deleting unit that deletes, when the storing unit stores, in the first cache memory, the directory that was read from the second cache memory by the reading unit, the directory stored in the second cache memory.

8. A pipeline control method comprising:

entering, by a cache control device, alternately into a pipeline a load request for reading a directory that is received from a processor and a store request for rewriting a directory that is received from the processor; and

first determining, by the cache control device, when the load request is entered, whether a directory targeted by the load request is present by searching a second cache memory and a first cache memory in which the speed of reading and writing data is higher than the speed of reading and writing data in the second cache memory; and

reading, by the cache control device, the directory, when it is determined that the directory targeted by the load request is present; and

second determining, by the cache control device, when it is determined that the store request is entered, whether a directory targeted by the store request is present by searching the first cache memory; and

rewriting, by the cache control device, the directory when it is determined that the directory targeted by the store request is present in the first cache memory.

9. The pipeline control method according to claim 8, wherein

when it is determined that the directory targeted by the store request is not present in the first cache memory, the entering includes re-entering, the store request as a load request into a pipeline, and

the first determining includes receiving the load request that is re-entered at the re-entering, includes searching the second cache memory, and includes determining whether a directory targeted by the load request is present.

10. The pipeline control method according to claim 8, wherein, when it is determined that the directory targeted by the store request is not present in the first cache memory nor the second cache memory, the reading includes reading a directory targeted by the store request from a main memory.

11. The pipeline control method according to claim 10, further comprising storing, by the cache control device, the directory read at the reading in the first cache memory, when it is determined that the directory targeted by the load request or the directory targeted by the store request is not present in the first cache memory.

12. The pipeline control method according to claim 11, wherein, when it is determined that the directory targeted by the store request is not present in the first cache memory, the entering includes re-entering the store request into a pipeline after the directory is stored in the first cache memory at the storing.

13. The pipeline control method according to claim 8, further comprising:

third determining, by the cache control device, when it is determined the directory is not present in the first cache memory, whether a free entry is present in the first cache memory; and

selecting, by the cache control device, when it is determined that the free entry is not present in the first cache memory, an entry from the first cache memory; and

moving, by the cache control device, the selected entry to the second cache memory.

14. The pipeline control method according to claim 13, further comprising deleting, by the cache control device, when the directory that was read from the second cache memory is stored in the first cache memory, the directory stored in the second cache memory.