SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

• US 20140097402A1
• Filed: 11/11/2011
• Published: 04/10/2014
• Est. Priority Date: 06/03/2011
• Status: Abandoned Application

• Current Assignee: Tsinghua University
• Original Assignee: Tsinghua University
• Inventors: Wang, Jing, Guo, Lei
• Application Number:
  US13/376,750
• Publication Number:
  US 20140097402A1
• Time in Patent Office: Days
• US Class Current: 257/19
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (1100); a plurality of convex structures (1200) formed on the substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures (1200) is less than 50 nm in width; a plurality of floated films (1300), in which the floated films (1300) are partitioned into a plurality of sets, a channel layer is formed on a convex structure (1200) between the floated films (1300) in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and the cavity between the every two adjacent convex structures (1200) is filled with an insulating material (2000); and a gate stack (1400) formed on each channel layer.

Claims

1. A semiconductor structure, comprising:

a substrate;

a plurality of convex structures formed on the substrate, wherein every two adjacent convex structures are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures is less than 50 nm in width;

a plurality of floated films, wherein each floated film is formed between the every two adjacent convex structures and connected with tops of the every two adjacent convex structures, the floated films are partitioned into a plurality of sets, a channel layer is formed on a convex structure between the floated films in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and the cavity size between the every two adjacent convex structures is filled with an insulating material so as to produce a strain in each channel layer; and

a gate stack formed on each channel layer.

2. The semiconductor structure according to claim 1, wherein a width of each convex structure increases gradually from a middle part thereof to a top part thereof so that a cavity size between top parts of two adjacent convex structures is less than that between middle parts of the two adjacent convex structures.

3. The semiconductor structure according to claim 1, wherein each convex structure comprises a bottom layer and a top layer, the bottom layer is a Si layer, and the top layer is a Si_yGe_1-y layer or a Ge layer.

4. The semiconductor structure according to claim 1, wherein the plurality of floated films are formed by annealing the plurality of convex structures at a temperature of 300-1350 degrees Celsius in an ambient containing hydrogen.

5. The semiconductor structure according to claim 1, wherein the insulating material comprises at least one material selected from a group consisting of Si_xN_y, SiO₂, and SiO_xN_y.

6. The semiconductor structure according to claim 1, wherein the insulating material comprises:

a first insulating material; and

a second insulating material filled between the first insulating material and the convex structures and between the first insulating material and the substrate.

7. The semiconductor structure according to claim 6, wherein the first insulating material is Si_xN_y or SiO_xN_y, and the second insulating material is SiO₂.

8. The semiconductor structure according to claim 7, wherein the first insulating material is doped with C.

9. The semiconductor structure according to claim 1, further comprising:

a side wall of one or more layers formed on sides of the gate stack.

10. A method for forming a semiconductor structure, comprising steps of:

providing a substrate;

forming a plurality of convex structures on the substrate, wherein every two adjacent convex structures are separated by a cavity in a predetermined pattern, and the cavity size between every two adjacent convex structures is less than 50 nm in width;

filling the cavity between the every two adjacent convex structures with an insulating material;

forming a semiconductor film on tops of the plurality of convex structures, wherein a first part of the semiconductor film on the cavity is spaced apart from the substrate to form a plurality of floated films, wherein the plurality of floated films are partitioned into a plurality of sets;

doping the semiconductor film on a convex structure between the floated films in each set so that a channel layer is formed and the floated films on two sides of the channel layer are set as a source region and a drain region respectively; and

forming a gate stack on each channel layer.

11. The method according to claim 10, wherein a width of each convex structure increases gradually from a middle part thereof to a top part thereof so that a cavity size between top parts of two adjacent convex structures is less than that between middle parts of the two adjacent convex structures.

12. The method according to claim 10, wherein the plurality of floated films are formed by annealing the plurality of convex structures at a temperature of 300-1350 degrees Celsius in an ambient containing hydrogen.

13. The method according to claim 10, further comprising:

etching a second part of the semiconductor film on a convex structure between two adjacent sets of floated films so that the convex structure between two adjacent sets of floated films is used as an isolation portion.

14. The method according to claim 10, further comprising:

forming a side wall of one or more layers on sides of the gate stack.

15. The method according to claim 10, wherein the insulating material is at least one material selected from a group consisting of Si_xN_y, SiO₂, and SiO_xN_y.

16. The method according to claim 10, wherein the step of filling the cavity between the every two adjacent convex structures with an insulating material comprises:

oxidizing sides of the convex structures and an exposed part of the substrate to form a second insulating material; and

forming a first insulating material on the second insulating material by deposition.

17. The method according to claim 16, further comprising:

doping the first insulating material with C.

18. The method according to claim 16, wherein the first insulating material is Si_xN_y or a SiO_xN_y, and the second insulating material is SiO₂.

19. The method according to claim 10, wherein the step of forming a semiconductor film on the plurality of convex structures comprises:

forming the semiconductor film on the plurality of convex structures by epitaxy.

20. The method according to claim 10, wherein the step of forming a plurality of convex structures on the substrate comprises:

forming a first semiconductor layer on the substrate;

implanting Si or Ge ions into the first semiconductor layer to form an ion-implanted layer in the first semiconductor layer; and

selectively etching the first semiconductor layer to form the plurality of convex structures.