PLASMA DOPING A NON-PLANAR SEMICONDUCTOR DEVICE

• US 20140097487A1
• Filed: 10/09/2012
• Published: 04/10/2014
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Advanced Ion Beam Technology Incorporated
• Original Assignee: Advanced Ion Beam Technology Incorporated
• Inventors: YEN, Tzu-Shih, TANG, Daniel, CHENG, Tsungnan
• Granted Patent: US 9,006,065 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Claims

1. A method for plasma doping a non-planar semiconductor device comprising:

obtaining a substrate having a first non-planar semiconductor body formed thereon;

placing the substrate into a chamber;

forming a plasma in the chamber, the plasma containing dopant ions;

generating a first bias voltage to implant dopant ions into a region of the first non-planar semiconductor body; and

generating a second bias voltage to implant dopant ions into the region, wherein the first bias voltage and the second bias voltage are different.

2. The method of claim 1, wherein the region is at least one of a channel region, a source region, a drain region, a source extension region, and a drain extension region.

3. The method of claim 1, wherein the first bias voltage is greater than the second bias voltage.

4. The method of claim 3, wherein generating a first bias voltage is prior to generating a second bias voltage.

5. The method of claim 3, wherein generating a first bias voltage implants a first dopant ion species, wherein generating a second bias voltage implants a second dopant ion species, and wherein the first dopant ion species has a molecular mass that is greater than that of the second dopant ion species.

6. The method of claim 3, wherein generating a first bias voltage implants dopant ions at a first implant angle in the region, wherein generating a second bias voltage implants dopant ions at a second implant angle in the region, and wherein the first implant angle is smaller than the second implant angle.

7. The method of claim 1, wherein generating a first bias voltage implants a first dopant ion species, wherein generating a second bias voltage implants a second dopant ion species, and wherein the first dopant ion species has a molecular mass that is different from that of the second dopant ion species.

8. The method of claim 1, further comprising:

generating a third bias voltage to implant dopant ions into the region, wherein the third bias voltage is different from the first bias voltage and the second bias voltage.

9. The method of claim 1, wherein generating a first bias voltage implants dopant ions at a first implant angle in the region, wherein generating a second bias voltage implants dopant ions at a second implant angle in the region, and wherein the first implant angle and the second implant angle are different.

10. The method of claim 9, wherein the first non-planar semiconductor body has a height, and wherein the first bias voltage, the first implant angle, the second bias voltage, and the second implant angle are defined to achieve a dopant concentration uniformity in the region of 5% or less across the height.

11. The method of claim 1, further comprising:

forming a padding layer over and around the first non-planar semiconductor body prior to placing the substrate into the chamber.

12. The method of claim 11, wherein the first non-planar semiconductor body has a top surface, and wherein the padding layer is formed to a thickness of 0-10 nanometers above the top surface of the first non-planar semiconductor body.

13. The method of claim 1, further comprising:

forming a punch through stopper layer.

14. The method of claim 13, wherein the punch through stopper layer is formed in the substrate directly below the first non-planar semiconductor body.

15. The method of claim 13, wherein the first non-planar semiconductor body has a critical dimension and a height, and wherein the punch through stopper layer is formed in the first non-planar semiconductor body at a depth greater than the critical dimension and less than the height of the first non-planar semiconductor body.

16. The method of claim 15, wherein the first non-planar semiconductor device has a channel width, and wherein the channel width is approximately twice the depth of punch through stopper layer summed with the critical dimension.

17. The method of claim 15, wherein the first bias voltage, the first implant angle, the second bias voltage, and the second implant angle are defined to achieve a dopant concentration uniformity in the region of 5% or less across the depth of the punch through stopper layer.

18. The method of claim 15, wherein the first non-planar semiconductor body has a length and wherein the depth of the punch through stopper layer has a uniformity of 5% or less across the length of the first non-planar semiconductor body.

19. The method of claim 1, wherein the obtained substrate has a second non-planar semiconductor body formed thereon, wherein the first non-planar semiconductor body and the second non-planar semiconductor body each have a height, wherein the height of the first non-planar semiconductor body is approximately equal to the height of the second non-planar semiconductor body, and further comprising:

forming a first punch through stopper layer in the first non-planar semiconductor body at a first depth;

forming a second punch through stopper layer in the second non-planar semiconductor body at a second depth, wherein the first depth is different from the second depth, and wherein the first depth and the second depth are less than or equal to the heights of the first non-planar semiconductor body and the second non-planar semiconductor body;

generating a third bias voltage to implant dopant ions into a region of the second non-planar semiconductor body; and

generating a forth bias voltage to implant dopant ions into the region of the second non-planar semiconductor body, wherein the third bias voltage and the forth bias voltage are different.

20. The method of claim 19, wherein the first non-planar semiconductor body and the second non-planar semiconductor body each have a critical dimension, wherein the first non-planar semiconductor body forms a first non-planar semiconductor device having a first channel width and the second non-planar semiconductor body forms a second non-planar semiconductor device having a second channel width, and wherein the first channel width is approximately twice the first depth summed with the critical dimension of the first non-planar semiconductor body and the second channel width is approximately twice the second depth summed with the critical dimension of the second non-planar semiconductor body.

21. The method of claim 1, further comprising:

annealing the first non-planar semiconductor body.

22. The method of claim 1, wherein the first non-planar semiconductor body is one of a fin, a nanowire, and a vertical array of nanowires.

23. The method of claim 1, wherein the non-planar semiconductor device is one of a FinFET device, a non-planar multi-gate transistor device, or a non-planar nano-wire transistor device.

24. A non-planar semiconductor device comprising:

a non-planar semiconductor body disposed on a substrate; and

a punch through stopper layer, wherein the non-planar semiconductor body has a critical dimension and a height, wherein the punch through stopper layer is disposed at a depth that is greater than the critical dimension and less than the height, and wherein the non-planar semiconductor body has a channel region, a source region, a drain region, a source extension region, and a drain extension region disposed above the punch through stopper layer.

25. The non-planar semiconductor device of claim 24, further comprising a channel width, wherein the channel width is approximately equal to twice the depth of the punch through stopper layer summed with the critical dimension of the non-planar semiconductor body.

26. The non-planar semiconductor device of claim 24, wherein the channel region, the source region, the drain region, the source extension region, and the drain extension region each have a dopant concentration uniformity of 5% or less across the depth.

27. The non-planar semiconductor device of claim 24, further comprising:

an interface between the punch through stopper layer and the channel region, the source region, the drain region, the source extension region, and the drain extension region, wherein at least one of the channel region, the source region, the drain region, the source extension region, and the drain extension region have a sheet resistance that increases by at least 3 orders of magnitude over a 3 nm thickness at the interface.

28. The non-planar semiconductor device of claim 24, further comprising:

a gate dielectric layer disposed over the channel region and a gate electrode disposed over the gate dielectric layer.

29. A non-transitory computer-readable storage medium containing computer executable instructions for plasma doping a non-planar semiconductor device, the computer executable instructions comprising instructions for:

placing a substrate having a non-planar semiconductor body formed thereon into a chamber;

forming a plasma in the chamber, the plasma containing dopant ions;

generating a first bias voltage to implant dopant ions into a region of the non-planar semiconductor body; and

generating a second bias voltage to implant dopant ions into the region, wherein the first bias voltage and the second bias voltage are different.