TEST METHOD AND TEST ARRANGEMENT
First Claim
1. A test method, comprising:
- providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and
applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
2 Assignments
0 Petitions
Accused Products
Abstract
A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
-
Citations
29 Claims
-
1. A test method, comprising:
-
providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. A test method, comprising:
-
providing a workpiece, the workpiece comprising a transistor to be tested, the transistor comprising a plurality of cells electrically connected in parallel, each cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying a plurality of test potentials to at least the at least one additional electrode of the cells to detect defective cells among the plurality of cells. - View Dependent Claims (24, 25, 26, 27)
-
-
28. A test arrangement, comprising:
-
a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region, at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and a test device configured to apply at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
-
-
29. A test method, comprising:
-
providing a semiconductor device to be tested, the semiconductor device being configured as a diode and comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region, at least one second terminal electrode region, and at least one electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region and the at least one second terminal electrode region; and applying at least one electrical test potential to at least the at least one electrode to detect defects in the at least one device cell.
-
Specification