METHOD AND APPARATUS OF PROBABILISTIC PROGRAMMING MULTI-LEVEL MEMORY IN CLUSTER STATES OF BI-STABLE ELEMENTS

• US 20140098602A1
• Filed: 12/12/2013
• Published: 04/10/2014
• Est. Priority Date: 05/06/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wu, Wenqing, Yuen, Kendrick Hoy Leong, Zhu, Xiaochun, Kang, Seung Hyuk, Nowak, Matthew Michael, Levin, Jeffrey Alexander, Gilmore, Robert P., Yu, Nicholas Ka Ming
• Granted Patent: US 9,135,976 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 11/5607 using magnetic storage elements

Abstract

A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Claims

1. A method of programming a resistance through a cluster of bi-stable switching elements, comprising:

detecting a state of the resistance through the cluster of bi-stable switching elements;

determining at least one programming current attribute based on the detected state;

applying the programming current with said at least one determined programming current attribute; and

iterating the above steps, until a given programming completion state is reached.

2. The method of claim 1, further comprising counting a number of iterations of iterating the above steps, and wherein one programming completion state is a timeout equal to a given number of the iterations.

3. The method of claim 1, wherein one programming completion state is said detecting a state of the resistance meeting a given resistance value.

4. The method of claim 1, wherein the at least one programming current attribute includes a current direction.

5. The method of claim 1, wherein the at least one programming current attribute includes a current magnitude.

6. The method of claim 1, wherein the at least one programming current attribute includes an analog waveform attribute.

7. The method of claim 1, further comprising counting a number of iterations of iterating the above steps, and wherein one programming completion state is the number of iterations reaching a given timeout, and another programming completion state is detecting a state of the resistance meeting a given resistance value.

8. The method of claim 7, wherein the method further comprises detecting a difference between the detected state of the resistance and a target resistance state, and wherein the method further comprises determining the timeout based on a given bit error rate and a switching characteristic of the bi-stable switching elements that, within the number of iterations represented by the given timeout, a probability of the difference between the resistance state and the target resistance state of the cluster of the bi-stable switching elements provides a bit error rate no larger than the given bit error rate.

9. A probabilistic resistive memory to store a data, comprising:

a resistive element cluster having bi-stable elements, each bi-stable element configured to switch in response to a programming current having at least one parameter, between a first resistance state of at least two resistance states and a second resistance state of the at least two resistance states, with a switching probability determined by a value of at least one parameter of the programming current; and

a probabilistic programming controller to detect a cluster resistance state of the resistive element cluster and to inject a programming current through the resistive element cluster, with the value of the at least one parameter determining the switching probability to be less than one.

10. The probabilistic resistive memory of claim 9, wherein the resistive element cluster has N bi-stable elements the data is an M-bit data, M being at least two, and wherein N is at least three.

11. The probabilistic resistive memory of claim 9, wherein the bi-stable switching elements are configured to switch from the first resistance state to the second resistance state in response to a programming current in a given forward direction, and to switch from the second resistance state to the first resistance state in response to a programming current in a given reverse direction opposite the given forward direction.

12. The probabilistic resistive memory of claim 11, wherein the probabilistic programming controller is configured to compare the cluster resistance state to a target resistance state corresponding to the data, to inject the programming current in the forward direction in response to the cluster resistance state being below the target resistance state, and to inject the programming current in the given reverse direction in response to the cluster resistance state being above the target resistance state.

13. The probabilistic resistive memory of claim 12, wherein the probabilistic programming controller is configured to detect an occurrence of a given termination condition, and wherein the probabilistic programming controller is configured to repeat the detecting the cluster resistance state and the injecting the programming current through the resistive element cluster until detecting the given termination condition.

14. The probabilistic resistive memory of claim 13, wherein the probabilistic programming controller is configured to detect a programming pulse count associated with a number of repetitions of the detecting the cluster resistance state and the injecting the programming current.

15. The probabilistic resistive memory of claim 13, wherein one given termination condition is a programming complete condition occurring when the comparing indicates the cluster resistance state meets the target resistance state within a given criterion.

16. The probabilistic resistive memory of claim 13, wherein one given termination condition is a programming complete condition occurring when the comparing indicates the programming pulse count meets a given timeout value.

17. The probabilistic resistive memory of claim 16, wherein the cluster comprises N bi-stable elements, wherein the data is a 1-bit data, wherein N is 1, and wherein the probabilistic programming controller current sets the value of the at least one parameter to determine the switching probability to be a value less than one that optimizes an average programming delay.

18. The probabilistic resistive memory of claim 9, wherein the probabilistic resistive memory is integrated in at least one semiconductor die.

19. The probabilistic resistive memory of claim 18, further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the probabilistic resistive memory is integrated.

20. A communication device comprising:

an antenna;

a wireless controller coupled to the antenna;

an integrated circuit, coupled to the wireless controller, the integrated circuit having a processing unit and a probabilistic resistive memory coupled to the processing unit, to store data; and

an input device coupled to the integrated circuit,

wherein the probabilistic resistive memory of the integrated circuit comprises;

a cluster of bi-stable elements, each bi-stable element configured to switch in response to a programming current, between a first resistance state of at least two resistance states and a second resistance state of the at least two resistance states, with a switching probability determined by a value of at least one parameter of the programming current; and

a probabilistic programming controller to detect a cluster resistance state of the cluster of bi-stable elements and to inject a programming current through the resistive element cluster, with the value of the at least one parameter determining the switching probability to be less than one.