DIGITALLY CONTROLLED JITTER INJECTION FOR BUILT IN SELF-TESTING (BIST)

• US 20140098843A1
• Filed: 10/04/2012
• Published: 04/10/2014
• Est. Priority Date: 10/04/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kong, Xiaohua, Zhu, Zhi, Dang, Vannam
• Granted Patent: US 8,811,458 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: H04B 17/104 of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04B 17/11 for calibration
• CPC Class Codes: H04B 17/16 Test equipment located at the transmitter
• CPC Class Codes: H04B 17/19 Self-testing arrangements
• CPC Class Codes: H04L 1/205 jitter monitoring

Abstract

A digitally controlled jitter injection apparatus for built in self-testing includes a transceiver circuit having a transmitter circuit and a receiver circuit. The digitally controlled jitter injection apparatus also includes a generator that generates a composite jitter including multi-tone jitter components. The digitally controlled jitter injection apparatus also includes a processor operable to digitally inject the composite jitter into a receiver circuit and/or a transmitter circuit of the transceiver circuit.

Claims

1. An apparatus, comprising:

a transceiver circuit comprising;

a generator configured to generate a composite jitter including a plurality of multi-tone jitter components; and

a processor operable to digitally inject the composite jitter into a receiver circuit and/or a transmitter circuit of the transceiver circuit.

2. The apparatus of claim 1, in which the processor is further operable to inject the plurality of multi-tone jitter components within a clock and data recovery loop of the receiver circuit.

3. The apparatus of claim 1, in which the processor is further operable to inject the plurality of multi-tone jitter components within a phase-locked loop (PLL) based clock and data recovery loop of the receiver circuit.

4. The apparatus of claim 1, in which the processor is further operable to inject the plurality of multi-tone jitter components within a phase interpolator based clock and data recovery loop of the receiver circuit.

5. The apparatus of claim 1, in which the composite jitter comprises a phase domain based composite jitter or a frequency domain based composite jitter.

6. The apparatus of claim 1, in which the generator comprises a predefined lookup table of composite jitter parameters and/or a processor for implementing a software configuration to generate the composite jitter parameters.

7. The apparatus of claim 6, in which the predefined lookup table of composite jitter parameters comprises a phase domain based look-up table and/or a frequency domain based look-up table.

8. The apparatus of claim 1, in which the receiver circuit, the transmitter circuit or the transceiver circuit is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

9. A method of self-testing a transceiver circuit, comprising:

generating a composite jitter including a plurality of multi-tone jitter components; and

digitally injecting the composite jitter into a receiver circuit and/or a transmitter circuit of the transceiver circuit.

10. The method of claim 9, further comprising:

driving the plurality of multi-tone jitter components into a receiver communication path injection point.

11. The method of claim 9, further comprising:

accessing a lookup table comprising a set of frequency and/or phase domain based composite jitter parameters; and

driving the frequency domain based composite jitter parameters and/or the phase domain based composite jitter parameters into a first receiver communication path injection point and/or a second receiver communication path injection point.

12. The method of claim 9, further comprising integrating the transceiver circuit into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

13. A transceiver circuit, comprising:

means for generating a composite jitter including a plurality of multi-tone jitter components; and

means for digitally injecting the composite jitter into a receiver circuit and/or a transmitter circuit of the transceiver circuit.

14. The transceiver circuit of claim 13, in which the digitally injecting means further comprises means for injecting the plurality of multi-tone jitter components within a clock and data recovery loop of the receiver circuit.

15. The transceiver circuit of claim 13, in which the digitally injecting means further comprises means for injecting the plurality of multi-tone jitter components within a phase-locked loop (PLL) based clock and data recovery loop of the receiver circuit.

16. The transceiver circuit of claim 13, in which the digitally injecting means further comprises means for injecting the plurality of multi-tone jitter components within a phase interpolator based clock and data recovery loop of the receiver circuit.

17. The transceiver circuit of claim 13, in which the transceiver circuit is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

18. A computer program product for self-testing a transceiver circuit, comprising:

a computer-readable medium having non-transitory program code recorded thereon, the program code comprising;

program code to generate a composite jitter including a plurality of multi-tone jitter components; and

program code to digitally inject the composite jitter into a receiver circuit and/or a transmitter circuit of the transceiver circuit.

19. The computer program product of claim 18, in which the program code further comprises code to inject the plurality of multi-tone jitter components within a clock and data recovery loop of the receiver circuit.

20. The computer program product of claim 18, in which the program code further comprises code to inject the plurality of multi-tone jitter components within a phase-locked loop (PLL) based clock and data recovery loop of the receiver circuit.