COMPOSITE FINITE FIELD MULTIPLIER
First Claim
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1. A composite finite field multiplier, comprising:
- an input port, configured to input an operand a(x), an operand b(x), an operand c(x), an irreducible polynomial p(x) selected over the GF(2n) field, an irreducible polynomial q(x) selected over the GF((2n)m) field and a control signal k;
a GF(2n) standard basis multiplier, configured to implement the multiplication (a(x)×
b(x)×
c(x))mod(p(x)) of the three operands a(x), b(x) and c(x) on the standard basis over GF(2n);
a GF(2n) look-up table multiplier, configured to implement the multiplication (a(x)d×
b(x)×
c(x))mod(p(x)) of the three operands a(x), b(x) and c(x) based on the look-up table over GF(2n);
a GF((2n)2) multiplier, comprising a first processor and a scheduler interconnected with each other;
the first processor is configured to implement the multiplication (a(x)×
b(x)×
c(x))mod(q(x)) of the three operands a(x), b(x) and c(x) over GF((2n)2);
when processing the addition operation over the GF(2n) field, using an XOR gate circuit included in the first processor to obtain an intermediate calculation result, while when processing the multiplication over the GF(2n) field, the scheduler calls the GF(2n) look-up table multiplier or GF(2n) standard basis multiplier to obtain an intermediate calculation result;
a controller, configured to parse the control signal k and control the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier based on the parsing result;
an output port, configured to output the results;
wherein the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier;
the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier.
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Abstract
A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier; the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier. By using the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2n)m).
6 Citations
7 Claims
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1. A composite finite field multiplier, comprising:
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an input port, configured to input an operand a(x), an operand b(x), an operand c(x), an irreducible polynomial p(x) selected over the GF(2n) field, an irreducible polynomial q(x) selected over the GF((2n)m) field and a control signal k; a GF(2n) standard basis multiplier, configured to implement the multiplication (a(x)×
b(x)×
c(x))mod(p(x)) of the three operands a(x), b(x) and c(x) on the standard basis over GF(2n);a GF(2n) look-up table multiplier, configured to implement the multiplication (a(x)d×
b(x)×
c(x))mod(p(x)) of the three operands a(x), b(x) and c(x) based on the look-up table over GF(2n);a GF((2n)2) multiplier, comprising a first processor and a scheduler interconnected with each other;
the first processor is configured to implement the multiplication (a(x)×
b(x)×
c(x))mod(q(x)) of the three operands a(x), b(x) and c(x) over GF((2n)2);
when processing the addition operation over the GF(2n) field, using an XOR gate circuit included in the first processor to obtain an intermediate calculation result, while when processing the multiplication over the GF(2n) field, the scheduler calls the GF(2n) look-up table multiplier or GF(2n) standard basis multiplier to obtain an intermediate calculation result;a controller, configured to parse the control signal k and control the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier based on the parsing result; an output port, configured to output the results; wherein the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier; the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier. - View Dependent Claims (3, 4, 5, 6, 7)
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2. (canceled)
Specification
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Current AssigneeSouth China University of Technology
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Original AssigneeSouth China University of Technology
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InventorsTang, Shaohua, Yi, Haibo
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current708/523
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CPC Class CodesG06F 17/10 Complex mathematical operat...G06F 2207/7209 Calculation via subfield, i...G06F 7/724 Finite field arithmetic for...
