TWO-WIRE COMMUNICATION PROTOCOL ENGINE

• US 20140101351A1
• Filed: 10/25/2013
• Published: 04/10/2014
• Est. Priority Date: 10/05/2012
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Kessler, Martin, Hooper, William, Lahr, Lewis F., Giancioppo, Michael
• Granted Patent: US 9,448,959 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G06F 13/4273 using a clocked protocol
• CPC Class Codes: H04B 3/50 Systems for transmission between fixed stations via two-conductor transmission lines H04B3/54 takes precedence
• CPC Class Codes: H04L 1/16 in which the return channel carries supervisory signals, e.g. repetition request signals
• CPC Class Codes: H04L 2001/0093 Point-to-multipoint

Abstract

In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.

Claims

1. An integrated circuit, comprising:

a two-wire communication protocol engine configured to manage control and data transmissions according to a two-wire communication protocol in a bi-directional, multi-node bus system, wherein the two-wire communication protocol engine comprises a state machine that allows for synchronized updates of configuration data across the bus system, wherein the multi-node bus system comprises at least one master node and a plurality of slave nodes interconnected on the bus system using a twisted wire pair bus to connect each node to a next node, wherein each of the slave nodes can write to the bus, read from the bus, and perform both read and write operations on the bus.

2. The integrated circuit according to claim 1, wherein the slave nodes can be powered over the twisted wire pair bus.

3. The integrated circuit according to claim 1, wherein the two-wire communication protocol includes a downstream portion and an upstream portion, wherein a control frame and downstream data are transmitted from the master node in the downstream portion, and wherein a response frame and upstream data are transmitted to the master node in the upstream portion, wherein a synchronization pattern at a beginning of the control frame is used as a time base by each slave node.

4. The integrated circuit according to claim 3, wherein the two-wire communication protocol uses clock-first transition on zero Differential Manchester coding, wherein the synchronization pattern is encoded using a modification of the Differential Manchester coding.

5. The integrated circuit according to claim 4, wherein the two-wire communication protocol engine includes a decoder block, wherein the decoder block detects the synchronization pattern using a clock recovered from the twisted wire pair bus.

6. The integrated circuit according to claim 3, wherein the downstream portion and the upstream portion each comprises 1024 bits, wherein the control frame and the response frame each comprises 64 bits, wherein a first 16 bits of each of the control frame and the response frame comprises the synchronization pattern.

7. The integrated circuit according to claim 3, wherein the two-wire communication protocol engine includes a scrambler that scrambles a portion of the data transmitted over the twisted wire pair, wherein the synchronization pattern and a frame count in the control frame and the response frame are not scrambled.

8. The integrated circuit according to claim 7, wherein the scrambler uses a linear feedback shift register (LSFR) to generate a pseudo-random bit-stream to scramble the portion of the data.

9. The integrated circuit according to claim 1, wherein the state machine transitions to a first state upon broadcasting a new structure write to the plurality of slave nodes, wherein a counter in the state machine is set to a predetermined non-zero value upon transition to the first state, wherein the counter decrements on an acknowledgement received from a last one of the slave nodes, wherein the state machine transitions to a second state when the counter reaches zero, wherein the new structure is applied while in the second state.

10. The integrated circuit according to claim 9, wherein state machines at corresponding slave nodes transition to the first state on receiving the new structure write broadcast, wherein respective counters are set to the predetermined non-zero value, wherein the respective counters decrement in the first state, wherein the state machines at corresponding slave nodes transition to a second state when the counter reaches zero, wherein the new structure is applied while in the second state.

11. The integrated circuit according to claim 1, wherein the master node is configured with a first number of downstream portions to transmit to the slave nodes and a first number of upstream portions to receive from the slave nodes, wherein the slave nodes are configured with a second number of downstream portions to retransmit down the twisted wire pair, a third number of downstream portions to consume, a second number of upstream portions to retransmit up the twisted wire pair, and a third number of upstream portions to transmit data, wherein each slave node accepts changes to the configuration substantially simultaneously.

12. The integrated circuit according to claim 1, wherein the two-wire communication protocol engine comprises an interrupt state machine that forms part of a distributed interrupt system across the master node and the plurality of slave nodes, wherein the master node signals an interrupt to a host controller after receiving the interrupt from one of the slave nodes.

13. The integrated circuit according to claim 12, wherein the master node performs a read of the one of the slave nodes to acquire details on the interrupt, wherein the details are stored locally on the master node, wherein the master node clears the interrupt in the slave node automatically.

14. The integrated circuit according to claim 13, wherein the host controller reads two registers on the master node to get the details, wherein one of the reads automatically clears the interrupt in the master node.

15. A method for facilitating communication between a master node and a plurality of slave nodes, comprising:

generating clock, synchronization and framing signals in a two-wire communication protocol for the plurality of slave nodes;

facilitating bi-directional transfer of data using a twisted wire pair bus to connect each node to the next node;

synchronizing updates of configuration data using a state machine; and

powering the slave nodes over the twisted wire pair bus.

16. The method of claim 15, further comprising:

transmitting a control frame and downstream data from the master node in a downstream portion of the two-wire communication protocol, wherein a synchronization pattern at a beginning of the control frame is used as a time base by each slave node; and

receiving a response frame and upstream data from the slave nodes in an upstream portion of the two-wire communication protocol.

17. The method of claim 15, further comprising:

transitioning to a first state upon broadcasting a new structure write to the plurality of slave nodes;

setting a counter to a predetermined non-zero value;

decrementing the counter upon each acknowledgement received from the plurality of slave nodes;

transitioning to a second state when the counter reaches zero; and

applying the new structure while in the second state.

18. The method of claim 15, further comprising:

receiving an interrupt from a slave node;

signaling the interrupt to a host controller;

reading the slave node to acquire details on the interrupt;

storing the details locally on the master node; and

clearing the interrupt in the slave node automatically.

19. The method of claim 18, wherein the host controller reads two registers on the master node to get the details, wherein one of the reads automatically clears the interrupt in the master node.

20. The method of claim 15, further comprising scrambling a portion of the data transmitted over the twisted wire pair.