APPARATUS AND METHOD FOR LOW POWER LOW LATENCY HIGH CAPACITY STORAGE CLASS MEMORY
First Claim
Patent Images
1. A method for implementing enhanced solid-state storage performance comprising:
- providing a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory; and
selectively allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size.
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Abstract
A method and a storage system are provided for implementing enhanced solid-state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory, for example, Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.
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Citations
32 Claims
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1. A method for implementing enhanced solid-state storage performance comprising:
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providing a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory; and selectively allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An apparatus for implementing enhanced solid-state storage performance comprising:
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a direct attached dual in line memory (DIMM) card, said DIMM card containing dynamic random access memory (DRAM), and at least one non-volatile memory;
Phase Change memory (PCM) and NAND flash memory;an eSCM processor coupled to said DRAM, and said at least one non-volatile memory on said DIMM card, and said eSCM processor, selectively allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. An enhanced solid-state storage class memory (eSCM) system comprising:
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a dynamic random access memory (DRAM), at least one non-volatile memory; a processor coupled to said DRAM, and said at least one non-volatile memory;
said processor allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size. - View Dependent Claims (27, 28, 29, 30, 31, 32)
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Specification