APPARATUS AND METHOD FOR LOW POWER LOW LATENCY HIGH CAPACITY STORAGE CLASS MEMORY

• US 20140101370A1
• Filed: 10/08/2012
• Published: 04/10/2014
• Est. Priority Date: 10/08/2012
• Status: Abandoned Application

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: Chu, Frank R., Franca-Neto, Luiz M., Tsai, Timothy K., Wang, Qingbo
• Application Number:
  US13/647,273
• Publication Number:
  US 20140101370A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and a storage system are provided for implementing enhanced solid-state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory, for example, Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Claims

1. A method for implementing enhanced solid-state storage performance comprising:

providing a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory; and

selectively allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size.

2. The method as recited in claim 1 wherein selectively allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size includes selectively partitioning data among the DRAM, and the at least one non-volatile memory.

3. The method as recited in claim 1 includes performing a read operation where part of the requested data is read from DRAM with simultaneously fetching parts of requested data from the at least one non-volatile memory.

4. The method as recited in claim 1 wherein providing the DRAM and the at least one non-volatile memory includes providing Phase Change memory (PCM) and NAND flash memory.

5. The method as recited in claim 4 includes providing an eSCM processor on said DIMM card with said DRAM, said PCM, and said NAND flash memory, and

using said eSCM processor, selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance.

6. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes selectively migrating data among said DRAM, said PCM, and said NAND flash memory based upon data set sizes.

7. The method as recited in claim 6 further includes selectively migrating data among said DRAM, said PCM, and said NAND flash memory based upon frequency of use.

8. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes writing first to said NAND flash memory and selectively moving data to at least one of said PCM, and said DRAM.

9. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes buffering data being written to said DRAM, before committing to said NAND flash memory;

and selectively maintaining said data committed in said NAND flash memory or selectively moving data committed to said NAND flash memory to at least one of said DRAM and said PCM.

10. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes presenting a memory interface to a second computer system, said second computer system including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory.

11. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes reading data from any of said DRAM, said PCM, and said NAND flash memory.

12. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes selectively allocating data primarily in said non-volatile memory including said PCM, and said NAND flash memory.

13. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes using said PCM primarily for storing relatively middle sized data sets.

14. The method as recited in claim 5 wherein selectively moving data among said DRAM, said PCM, and said NAND flash memory for enabling enhanced latency and throughput performance includes using said NAND flash memory primarily for storing relatively large data sets.

15. An apparatus for implementing enhanced solid-state storage performance comprising:

a direct attached dual in line memory (DIMM) card, said DIMM card containing dynamic random access memory (DRAM), and at least one non-volatile memory;

Phase Change memory (PCM) and NAND flash memory;

an eSCM processor coupled to said DRAM, and said at least one non-volatile memory on said DIMM card, and

said eSCM processor, selectively allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size.

16. The apparatus as recited in claim 15 includes control code stored on a computer readable medium, and wherein said eSCM processor uses said control code for implementing enhanced solid-state storage performance.

17. The apparatus as recited in claim 15 wherein said wherein said at least one non-volatile memory includes at least one of a Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash memory.

18. The apparatus as recited in claim 15 wherein said at least one non-volatile memory includes Phase Change memory (PCM) and NAND flash memory.

19. The apparatus as recited in claim 18 includes said eSCM processor, using an intelligent data size detection algorithm for selectively moving data among said DRAM, said PCM, and said NAND flash memory.

20. The apparatus as recited in claim 19 wherein said eSCM processor, selectively moving data among said DRAM, said PCM, and said NAND flash memory includes said eSCM processor writing to said NAND flash memory and selectively moving data to said PCM.

21. The apparatus as recited in claim 19 wherein said eSCM processor, selectively moving data among said DRAM, said PCM, and said NAND flash memory includes said eSCM processor selectively migrating data among said DRAM, said PCM, and said NAND flash memory according to data set sizes.

22. The apparatus as recited in claim 19 wherein said eSCM processor, selectively moving data among said DRAM, said PCM, and said NAND flash memory includes said eSCM processor selectively allocating data primarily in non-volatile memory including said PCM, and said NAND flash memory.

23. The apparatus as recited in claim 19 wherein said eSCM processor, selectively moving data among said DRAM, said PCM, and said NAND flash memory includes said eSCM processor using said PCM primarily for storing relatively medium sized data sets.

24. The apparatus as recited in claim 19 wherein said eSCM processor, selectively moving data among said DRAM, said PCM, and said NAND flash memory includes said eSCM processor using said NAND flash memory primarily for storing high density large data sets.

25. The apparatus as recited in claim 15 includes a memory interface to a second computer system, said second computer system including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory coupled to said memory interface.

26. An enhanced solid-state storage class memory (eSCM) system comprising:

a dynamic random access memory (DRAM),

at least one non-volatile memory;

a processor coupled to said DRAM, and said at least one non-volatile memory;

said processor allocating data among the DRAM, and the at least one non-volatile memory based upon a data set size.

27. The eSCM system as recited in claim 26 wherein said at least one non-volatile memory includes Phase Change memory (PCM) and NAND flash memory.

28. The eSCM system as recited in claim 27 includes a direct attached dual in line memory (DIMM) card, said DIMM card containing said dynamic random access memory (DRAM), Phase Change memory (PCM) and NAND flash memory.

29. The eSCM system as recited in claim 26 includes a memory interface to a second computer system, said second computer system including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory coupled to said memory interface.

30. The eSCM system as recited in claim 26 includes a memory interface to another storage system including at least one of a Solid State drive (SSD), and a hard disk drive (HDD).

31. The eSCM system as recited in claim 26 wherein said at least one non-volatile memory includes at least one of a Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash memory.

32. The eSCM system as recited in claim 26 includes a memory interface to a second storage system including at least one of a Solid State drive (SSD), and a hard disk drive (HDD) and further includes said processor selectively migrating data among said DRAM, said PCM, said ReRAM, said STT-RAM and said NAND flash memory;

and said second storage system.