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Computer Cache System Providing Multi-Line Invalidation Messages

  • US 20140101390A1
  • Filed: 10/08/2012
  • Published: 04/10/2014
  • Est. Priority Date: 10/08/2012
  • Status: Active Grant
First Claim
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1. A computer architecture comprising:

  • a cache memory holding lines of data that may be individually invalidated;

    a processor for executing program instructions operating on data from the cache memory;

    a cache controller communicating with the cache memory and operating to;

    (a) detect access of cache lines by operations of the processor where the access requires a transmission of invalidation messages for coherent cache operation;

    (b) delay communication of the invalidation messages; and

    (c) collect multiple delayed invalidation messages in a single combined invalidation message and transmit the single combined invalidation message instead of multiple invalidation messages.

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