THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE

• US 20140103333A1
• Filed: 12/17/2012
• Published: 04/17/2014
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Liu, Xiang, Lee, Woobong
• Granted Patent: US 8,912,538 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

Embodiments of the present invention provide a thin film transistor array substrate, a method for manufacturing the same, a display panel and a display device. The method for manufacturing the thin film transistor array substrate comprises: sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively. According to technical solutions of the embodiments of the invention, it is possible that the manufacturing process of the metal oxide TFT array substrate is simplified, and the production cost of products is reduced.

Claims

1. A method for manufacturing a thin film transistor array substrate, comprising:

sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; and

patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively.

2. The method for manufacturing the thin film transistor array substrate of claim 1, wherein, the patterning of the first metal oxide layer, the second metal oxide layer and the source and drain metal layer comprises:

applying photoresist on the source and drain metal layer;

forming a completely-removed region, a completely-retained region corresponding to the source electrode and the drain electrode, and a partially-retained region corresponding to a channel area;

etching off the source and drain metal layer, the first metal oxide layer and the second metal oxide layer in the completely-removed region;

performing a photoresist ashing process so as to remove the photoresist in the partially-retained region;

etching off the source and drain metal layer in the partially-retained region;

etching off the second metal oxide layer in the partially-retained region; and

removing the photoresist in the completely-retained region.

3. The method for manufacturing the thin film transistor array substrate of claim 2, wherein, after formation of the source electrode and the drain electrode, the method further comprises:

repairing a surface of the active layer at the channel area.

4. The method for manufacturing the thin film transistor array substrate of claim 1, wherein, the manufacturing method comprises:

prior to deposition of the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, forming patterns of a gate electrode and a gate scan line on a substrate and forming a gate insulating layer on the substrate with the patterns of the gate electrode and the gate scan line formed thereon;

simultaneously with the formation of the source electrode and the drain electrode, forming a data line with the source and drain metal layer, the data line being connected to the source electrode; and

after patterning of the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, forming a pattern of a passivation layer including a contact hole on the substrate with the patterns of the source electrode, the drain electrode and the data line formed thereon, and forming a pixel electrode which is connected to the drain electrode through the contact hole on the passivation layer.

12. The method for manufacturing the thin film transistor array substrate of claim 2, wherein, the manufacturing method comprises:

prior to deposition of the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, forming patterns of a gate electrode and a gate scan line on a substrate and forming a gate insulating layer on the substrate with the patterns of the gate electrode and the gate scan line formed thereon;

simultaneously with the formation of the source electrode and the drain electrode, forming a data line with the source and drain metal layer, the data line being connected to the source electrode, and

after patterning of the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, forming a pattern of a passivation layer including a contact hole on the substrate with the patterns of the source electrode, the drain electrode and the data line formed thereon, and forming a pixel electrode which is connected to the drain electrode through the contact hole on the passivation layer.

13. The method for manufacturing the thin film transistor array substrate of claim 3, wherein, the manufacturing method comprises:

prior to deposition of the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, forming patterns of a gate electrode and a gate scan line on a substrate and forming a gate insulating layer on the substrate with the patterns of the gate electrode and the gate scan line formed thereon;

simultaneously with the formation of the source electrode and the drain electrode, forming a data line with the source and drain metal layer, the data line being connected to the source electrode, and

after patterning of the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, forming a pattern of a passivation layer including a contact hole on the substrate with the patterns of the source electrode, the drain electrode and the data line formed thereon, and forming a pixel electrode which is connected to the drain electrode through the contact hole on the passivation layer.

5. A thin film transistor array substrate, comprising:

an active layer formed by a first metal oxide layer;

a buffer layer formed by a second metal oxide layer, conductivity of the buffer layer being larger than conductivity of the active layer, the buffer layer including a source-electrode buffer layer and a drain-electrode buffer layer; and

a source electrode and a drain electrode which are formed by a source and drain metal layer;

wherein, the source-electrode buffer layer is located between the active layer and the source electrode, and the drain-electrode buffer layer is located between the active layer and the drain electrode.

6. The thin film transistor array substrate of claim 5, wherein, the buffer layer includes at least two metal oxide layers, and with increasing of the distance from the active layer, conductivities of the metal oxide layers are gradually increased.

7. The thin film transistor array substrate of claim 5, further comprising:

a substrate,

a gate electrode and a gate scan line which is located on the substrate and formed by a gate metal layer;

a gate insulating layer located on the substrate with the gate electrode and the gate scan line formed thereon;

the active layer located on the gate insulating layer;

the source-electrode buffer layer and the drain-electrode buffer layer located on the active layer;

the source electrode and the drain electrode, which are located on the source-electrode buffer layer and the drain-electrode buffer layer, respectively;

a data line located in the same layer with the source electrode and the drain electrode and connected to the source electrode;

a passivation layer which is located on the substrate with the source electrode, the drain electrode and the data line formed thereon and includes a contact hole; and

a pixel electrode, which is located on the passivation layer and connected to the drain electrode through the contact hole.

8. The thin film transistor array substrate of claim 5, material for the buffer layer is amorphous IGZO.

9. The thin film transistor array substrate of claim 5, wherein, material for the active layer is amorphous IGZO, HIZO, IZO, a-InZnO, ZnO:

F, In₂O₃;

Sn, In₂O₃;

Mo, Cd₂SnO₄, ZnO;

Al, TiO₂;

Nb or Cd—

Sn—

O.

10. A display panel, comprising the thin film transistor array substrate of claim 5.

14. The thin film transistor array substrate of claim 6, further comprising:

a substrate,

a gate electrode and a gate scan line which is located on the substrate and formed by a gate metal layer;

a gate insulating layer located on the substrate with the gate electrode and the gate scan line formed thereon;

the active layer located on the gate insulating layer;

the source-electrode buffer layer and the drain-electrode buffer layer located on the active layer;

the source electrode and the drain electrode, which are located on the source-electrode buffer layer and the drain-electrode buffer layer, respectively;

a data line located in the same layer with the source electrode and the drain electrode and connected to the source electrode;

a passivation layer which is located on the substrate with the source electrode, the drain electrode and the data line formed thereon and includes a contact hole; and

a pixel electrode, which is located on the passivation layer and connected to the drain electrode through the contact hole.

15. The thin film transistor array substrate of claim 6, wherein, material for the buffer layer is amorphous IGZO.

16. The thin film transistor array substrate of claim 7, wherein, material for the buffer layer is amorphous IGZO.

17. The thin film transistor array substrate of claim 14, wherein, material for the buffer layer is amorphous IGZO.

18. The thin film transistor array substrate of claim 6, wherein, material for the active layer is amorphous IGZO, HIZO, IZO, a-InZnO, ZnO:

F, In₂O₃;

Sn, In₂O₃;

Mo, Cd₂SnO₄, ZnO;

Al, TiO₂;

Nb or Cd—

Sn—

O.

19. The thin film transistor array substrate of claim 7, wherein, material for the active layer is amorphous IGZO, HIZO, IZO, a-InZnO, ZnO:

F, In₂O₃;

Sn, In₂O₃;

Mo, Cd₂SnO₄, ZnO;

Al, TiO₂;

Nb or Cd—

Sn—

O.

20. The thin film transistor array substrate of claim 14, wherein, material for the active layer is amorphous IGZO, HIZO, IZO, a-InZnO, ZnO:

F, In₂O₃;

Sn, In₂O₃;

Mo, Cd₂SnO₄, ZnO;

Al, TiO₂;

Nb or Cd—

Sn—

O.

11. (canceled)