Random Doping Fluctuation Resistant FinFET

• US 20140103437A1
• Filed: 10/10/2013
• Published: 04/17/2014
• Est. Priority Date: 10/15/2012
• Status: Abandoned Application

• Current Assignee: Semiwise Limited
• Original Assignee: Semi Solutions LLC, Gold Standard Simulations Ltd (Synopsys Incorporated)
• Inventors: Kapoor, Ashok K., Strain, Robert J.
• Application Number:
  US14/051,163
• Publication Number:
  US 20140103437A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

An improved fin field-effect transistor (FinFET) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces FinFET random doping fluctuations when doping is used to control threshold voltage. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Three representative embodiments of the key structure are described in detail.

Claims

1. A transistor formed on a fin comprising:

a fin core having a first doping density; and

a channel region covering the fin core, the channel region having a second doping density that is less than the first doping density.

2. The transistor of claim 1, wherein the first doping density is between 10¹⁸/cm³ and 10²⁰/cm³ of donors for a PMOS transistor and acceptors for an NMOS transistor.

3. The transistor of claim 1, wherein the second doping density is less than 10¹⁷/cm³.

4. The transistor of claim 1, wherein the second doping density is less than 10¹⁶/cm³.

5. The transistor of claim 1, further comprising:

a stack of dielectric materials on the channel region.

6. The transistor of claim 5, wherein the stack of dielectric materials has an effective dielectric constant larger than 6.

7. The transistor of claim 1, further comprising a gate over the channel region, wherein the gate material is one of:

a metal, metal alloy or metallic compound.

8. The transistor of claim 1 wherein the channel region is an epitaxial sheathing layer, and the final thickness of the epitaxial sheathing layer is in the range of 5 nm to 15 nm.

9. The transistor of claim 1 wherein the fin is formed on a silicon wafer.

10. The transistor of claim 1 wherein the fin is a silicon-on-insulator fin.

11. A transistor formed on a fin comprising:

a fin core having a first doping density;

an epitaxial layer on the fin core, the epitaxial layer having a second doping density that is less than the first doping density;

source and drain regions formed in the epitaxial layer, the source and drain regions being separated to define a channel region between the source and drain regions;

a dielectric layer on the channel region; and

a gate on the dielectric layer.

12. The transistor of claim 11, wherein the first doping density is between 10¹⁸/cm³ and 10²⁰/cm³ of donors for a PMOS transistor and acceptors for an NMOS transistor.

13. The transistor of claim 11, wherein the second doping density is less than 10¹⁷/cm³.

14. The transistor of claim 11, wherein the second doping density is less than 10¹⁶/cm³.

15. The transistor of claim 11, wherein the dielectric layer comprises a stack of dielectric materials having an effective dielectric constant larger than 6.

16. The transistor of claim 11, wherein the gate material is one of:

a metal, metal alloy or metallic compound.

17. The transistor of claim 11 wherein the final thickness of the epitaxial layer is in the range of 5 nm to 15 nm.

18. The transistor of claim 11 wherein the fin is formed on a silicon wafer.

19. The transistor of claim 11 wherein the fin is a silicon-on-insulator fin.

20. The transistor of claim 11 wherein the source and drain regions each include source and drain extensions, respectively, formed in the epitaxial layer, the source and drain extensions being separated to define the channel region between the source and drain extensions.

21. A method formed on a fin comprising:

a) providing a fin core having a first doping density;

b) forming an epitaxial layer on the fin core, the epitaxial layer having a second doping density that is less than the first doping density;

c) forming an oxide on the epitaxial layer;

d) forming a gate on the epitaxial layer;

e) implanting source and drain extensions;

f) forming sidewall spacers adjacent the gate;

g) forming source and drains using implants, metal silicide formation or epitaxial enhancement or a combination of implants, metal silicide formation or epitaxial enhancement;

h) depositing a first inter-layer dielectric and planarizing to expose the gate.

22. The method of claim 21 wherein the oxide formed in c) is a gate oxide.

23. The method of claim 21 further comprising:

i) removing the gate formed in d) and the oxide between the sidewall spacers formed in c);

j) forming a dielectric between the spacers;

k) forming a metal gate over the dielectric.

24. The method of claim 23 further comprising forming a gate handle over the metal gate.

25. The method of claim 23 wherein the dielectric formed in j) is a high-K dielectric is a dielectric stack having a dielectric constant in excess of 6.

26. The method of claim 23, wherein the first doping density is between 10¹⁸/cm³ and 10²⁰/cm³ of donors for a PMOS transistor and acceptors for an NMOS transistor.

27. The method of claim 23, wherein the second doping density is less than 10¹⁷/cm³.

28. The method of claim 23, wherein the second doping density is less than 10¹⁶/cm³.

29. The method of claim 23 wherein the fin is formed on a silicon wafer.

30. The method of claim 23 wherein the fin is a silicon on insulator fin.

31. The method of claim 21 wherein the epitaxial layer of b) is grown at a temperature of less than 650°

C.

32. The method of claim 21 wherein all processes after a) are performed at temperatures of less than 650°

C.