SEMICONDUCTOR STRUCTURE AND METHOD OF GENERATING MASKS FOR MAKING INTEGRATED CIRCUIT

• US 20140103545A1
• Filed: 10/12/2012
• Published: 04/17/2014
• Est. Priority Date: 10/12/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Hui Yu, KUO, Feng Wei, KUAN, Jui-Feng, CHENG, Yi-Kan
• Granted Patent: US 9,053,255 B2
• Time in Patent Office: Days
• US Class Current: 257/786
• CPC Class Codes: G03F 1/38 Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 1/88 prepared by photographic processes for production of originals simulating relief
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2223/6638 Differential pair signal lines
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.

Claims

16. A method of simulating coupling capacitance variation of a plurality of conductive paths of the integrated circuit caused by misalignment of masks for making the plurality of conductive paths, the plurality of conductive paths is arranged in parallel, and the method comprising:

generating a table listing combinations of one or more predetermined conductive paths of the plurality of conductive paths and types of misalignment between a corresponding one of the masks against the remaining of the masks;

identifying a subset of combinations that do not correspond to shifting a corresponding conductive path of the plurality of conductive paths between two adjacent conductive paths of the plurality of conductive paths; and

calculating, by a hardware processor, a coupling capacitance value based on one combination of the subset of combinations.

17. The method of claim 16, wherein the calculation of the coupling capacitance value comprises:

calculating the coupling capacitance value of the conductive path under a condition that one of the masks has a predetermined level of misalignment against the remaining masks.

18. The method of claim 17, further comprising:

calculating another coupling capacitance value of the conductive path under another condition that the one of the masks has another predetermined level of misalignment against the remaining masks.

19. The method of claim 18, further comprising:

displaying, by a display unit, a column chart of a visualized presentation of the coupling capacitance value, the another coupling capacitance value, the predetermined level of misalignment, and the another predetermined level of misalignment.

20. A semiconductor structure comprising:

a first conductive path and a second conductive path configured to carry a first pair of differential signals representative of an in-phase signal;

a third conductive path and a fourth conductive path configured to carry a second pair of differential signals representative of a quadrature signal corresponding to the in-phase signal,

wherein the first, second, third, and fourth conductive paths extend along a first direction and are arranged according to an order, along a second direction perpendicular to the first direction, of the first, third, second, and fourth conductive paths, the first and second conductive paths are separated from the third and fourth conductive paths by an overall vertical distance.

1. A method of generating masks for making an integrated circuit, the masks comprising layout patterns corresponding to a first and second groups of conductive paths of the integrated circuit, and the method comprising:

determining, by a hardware processor, if a coupling capacitance value of a conductive path of the first and second groups of conductive paths is greater than a predetermined threshold value, the determination being performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment; and

modifying the layout patterns to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.

2. The method of claim 1, wherein the determination if the coupling capacitance value of the conductive path of the first and second groups of conductive paths is greater than the predetermined threshold value comprises:

calculating the coupling capacitance value of the conductive path under a condition that one of the masks has the predetermined level of mask misalignment against the remaining masks.

3. The method of claim 2, further comprising:

calculating another coupling capacitance value of the conductive path under another condition that one of the masks has another predetermined level of mask misalignment against the remaining masks.

4. The method of claim 3, further comprising:

displaying, by a display unit, a column chart of a visualized presentation of the coupling capacitance value, the another coupling capacitance value, the predetermined level of mask misalignment, the another predetermined level of mask misalignment, and the predetermined threshold value.

5. The method of claim 1, wherein the determination if the coupling capacitance value of the conductive path of the first and second groups of conductive paths is greater than the predetermined threshold value comprises:

generating a table listing combinations of one or more predetermined conductive paths of the first and second groups of conductive paths and types of mask misalignment between a corresponding one of the masks against the remaining of the masks;

identifying a subset of combinations that do not correspond to shifting a corresponding conductive path of the first and second groups of conductive paths between two adjacent conductive paths of the first and second groups of conductive paths; and

calculating the coupling capacitance value based on one combination of the subset of combinations.

6. The method of claim 1, wherein the first group of conductive paths including a first conductive path and a second conductive path, the second group of conductive paths including a third conductive path and a fourth conductive path, the first group of conductive paths and the second group of conductive paths extend along a first direction and are arranged according to an order, along a second direction perpendicular to the first direction, of the first, third, second, and fourth conductive paths, layout patterns for the first group of conductive paths are associated with a m-th conductive layer of the integrated circuit, mask patterns for the second group of conductive paths are associated to a (m+n)-th conductive layer of the integrated circuit, m is a positive integer, n is a non-negative integer, and the modification of the layout patterns comprises one or both of the following:

assigning the layout patterns corresponding to the first group of conductive paths to a (m+n+a)-th conductive layer of the integrated circuit, a is a positive integer; and

assigning the layout patterns corresponding to the second group of conductive paths to a (m−

b)-th conductive layer of the integrated circuit, b is a positive integer.

7. The method of claim 6, further comprising, after the performance of one or both the assignment of the layout patterns:

duplicating the layout patterns corresponding to the first group of conductive paths to one or more masks corresponding to one or more conductive layers above the first group of conductive paths; and

duplicating the layout patterns corresponding to the second group of conductive paths to one or more masks corresponding to one or more conductive layers below the second group of conductive paths.

8. The method of claim 6, further comprising, after the assignment of the layout patterns:

duplicating the layout patterns corresponding to the first group of conductive paths to one or more masks corresponding to one or more first conductive layers; and

duplicating the layout patterns corresponding to the second group of conductive paths to one or more masks corresponding to one or more second conductive layers,

wherein the one or more first conductive layers are arranged in an interleaving manner with respect to the one or more second conductive layers.

9. The method of claim 1, wherein the first group of conductive paths including a first conductive path and a second conductive path, the second group of conductive paths including a third conductive path and a fourth conductive path, the first and second groups of conductive paths extend along a first direction and are arranged according to an order, along a second direction perpendicular to the first direction, of the first, third, second, and fourth conductive paths, and the modification of the layout patterns comprises:

dividing the first conductive path into a first set of segments and dividing the second conductive path into a second set of segments;

dividing the third conductive path into a third set of segments and dividing the fourth conductive path into a fourth set of segments;

arranging layout patterns of the first, second, third, and fourth sets of segments to two different conductive layers of the integrated circuit in a manner that corresponding segments of the first and third sets of segments are in different conductive layers and corresponding segments of the second and fourth sets of segments are in different conductive layers.

10. The method of claim 9, wherein the layout patterns are arranged in a manner that the corresponding segments of the second and third sets of segments are in the same conductive layer.

11. The method of claim 9, wherein the layout patterns are arranged in a manner that the corresponding segments of the second and third sets of segments are in the different conductive layers.

12. The method of claim 9, wherein all segments of the first, second, third, and fourth sets of segments have a same predetermined segment length.

13. The method of claim 9, wherein all segments of the first, second, third, and fourth sets of segments have either a first predetermined segment length or a second predetermined segment length, and any two consecutive segments of the all segments have different segment lengths.

14. The method of claim 9, wherein the first group of conductive paths further including a first dummy conductive path, the second group of conductive paths further including a second dummy conductive path, the first group of conductive paths and the second group of conductive paths extend along the first direction and are arranged according to an order, along the second direction perpendicular to the first direction, of the second dummy conductive path, the first, third, second, and fourth conductive paths, and the first dummy conductive path, and the modification of the layout patterns comprises:

assigning mask patterns corresponding to the first and second dummy conductive paths in a manner that the first and second dummy conductive paths are in both of the two different conductive layers.

15. The method of claim 14, further comprising:

generating mask patterns for forming via plugs connecting the first and second dummy conductive paths in one of the two different conductive layers and the corresponding first and second dummy conductive paths in the other one of the two different conductive layers.

21. The semiconductor structure of claim 20, wherein the first and second conductive paths are in a conductive layer of the semiconductor structure, and the third and fourth conductive paths are in another conductive layer of the semiconductor structure.

22. The semiconductor structure of claim 20, wherein the first and second conductive paths are in a plurality of first conductive layers of the semiconductor structure, and the third and fourth conductive paths are in a plurality of second conductive layers of the semiconductor structure lower than the plurality of the first conductive layers.

23. The semiconductor structure of claim 20, wherein the first and second conductive paths are in a plurality of first conductive layers of the semiconductor structure, the third and fourth conductive paths are in a plurality of second conductive layers of the semiconductor structure interleaved with the plurality of the first conductive layers.

24. The semiconductor structure of claim 20, wherein:

the first conductive path includes a first set of segments;

the second conductive path includes a second set of segments;

the third conductive path includes a third set of segments; and

the fourth conductive path includes a fourth set of segments, corresponding segments of the first and third sets of segments being in two conductive layers, and corresponding segments of the second and fourth sets of segments being in the two conductive layers.

25. The semiconductor structure of claim 24, wherein the corresponding segments of the second and third sets of segments are in the same one of the two conductive layers.

26. The semiconductor structure of claim 24, wherein the corresponding segments of the second and third sets of segments are in different ones of the two conductive layers.

27. The semiconductor structure of claim 24, wherein all segments of the first, second, third, and fourth sets of segments have a same predetermined segment length.

28. The semiconductor structure of claim 24, wherein all segments of the first, second, third, and fourth sets of segments have either a first predetermined segment length or a second predetermined segment length, and any two consecutive segments of the all segments have different segment lengths.

29. The semiconductor structure of claim 28, wherein the first and third dummy conductive paths are positioned one over the other and connected by a plurality of via plugs, and the second and fourth dummy conductive paths are positioned one over the other and connected by another plurality of via plugs.

28-1. The semiconductor structure of claim 24, further comprising:

a first conductive dummy path and a second conductive dummy path in one of the two conductive layers and extending along the first direction, the first, second, third, and fourth conductive paths being horizontally between the first dummy conductive path and the second dummy conductive path; and

a third dummy conductive path and a fourth dummy conductive path in the other one of the two conductive layers and extending along the first direction, the first, second, third, and fourth conductive paths being horizontally between the third dummy conductive path and the fourth dummy conductive path.

30. A method of generating layout patterns for making a first and second conductive paths of an integrated circuit, the first and second conductive paths being in parallel along a predetermined direction, the method comprising:

dividing a first line pattern representative of the first conductive path into a first set of segments;

dividing a second line pattern representative of the second conductive path into a second set of segments;

grouping the first set of segments and the second set of segments into;

a first group of segments containing odd-ordered segments of the first set of segments and even-ordered segments of the second set of segments; and

a second group of segments containing even-ordered segments of the first set of segments and odd-ordered segments of the second set of segments;

assigning layout patterns of the odd-ordered segments in the first group of segments to a first mask;

assigning layout patterns of the even-ordered segments in the first group of segments to a second mask;

assigning layout patterns of odd-ordered segments in the second group of segments to a third mask; and

assigning layout patterns of even-ordered segments in the first group of segments to a fourth mask.

31. The method of claim 30, further comprising:

extending ends of the layout patterns of the segments for a length sufficient to accommodate via plug landing regions.