Load Transient, Reduced Bond Wires for Circuits Supplying Large Currents
First Claim
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1. A method to improve dynamic load transient performance of circuits supplying high current, comprising the following steps:
- (1) providing an electronic circuit supplying high currents and having parasitic resistances;
(2) including parasitic resistances in a separate loop for fast loop response;
(3) implementing stabilizing circuit within said fast loop response; and
(4) deploying separate pad for the fast loop response connected to feedback voltage VFB.
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Abstract
Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.
5 Citations
22 Claims
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1. A method to improve dynamic load transient performance of circuits supplying high current, comprising the following steps:
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(1) providing an electronic circuit supplying high currents and having parasitic resistances; (2) including parasitic resistances in a separate loop for fast loop response; (3) implementing stabilizing circuit within said fast loop response; and (4) deploying separate pad for the fast loop response connected to feedback voltage VFB. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances, comprising:
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a separate loop for fast transient response including the parasitic resistances; a separate pad for the loop for fast transient response; and a stabilizing circuit connected to said loop for fast transient response. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification