SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING THE SAME

• US 20140104953A1
• Filed: 10/14/2013
• Published: 04/17/2014
• Est. Priority Date: 10/15/2012
• Status: Active Grant

• Current Assignee: Amkor Technology Taiwan Limited (Amkor Technology Incorporated)
• Original Assignee: J-Devices Corporation (Amkor Technology Incorporated)
• Inventors: ITAKURA, Satoru, Katsumata, Akio, Umeki, Akihiro, Shiraishi, Yasushi, Abe, Junichiro
• Granted Patent: US 8,897,051 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G06F 3/00 Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Claims

1. A semiconductor storage device, comprising:

a controller package having a BGA terminal on a bottom surface thereof; and

one or a plurality of memory packages each including a plurality of semiconductor storage elements and mounted on the controller package;

wherein;

(A) the controller package includes;

a bottom substrate having the BGA terminal on a bottom surface thereof;

a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and

a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC, the controller providing an interface with an external system via the BGA terminal and controlling a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements;

wherein a memory terminal pattern for mounting the one or plurality of memory packages thereon is formed on a top surface of the controller package, the memory terminal pattern being connected to the controller; and

(B) the one or plurality of memory packages are mounted on, and electrically connected to, the memory terminal pattern.

2. A semiconductor storage device according to claim 1, wherein the controller includes:

an external interface interfacing with the external system; and

a core unit for controlling the read operation and the write operation;

wherein the external interface unit is supplied with a first power supply voltage from the power supply IC, and the core unit is supplied with a second power supply voltage from the power supply IC.

3. A semiconductor storage device according to claim 2, wherein:

the controller further includes a memory interface unit for interfacing with the semiconductor storage elements;

the semiconductor storage elements each include a controller interface unit for interfacing with the controller and a memory core unit for storing information; and

the memory interface unit and the controller interface unit are each supplied with a third power supply voltage from the power supply IC.

4. A semiconductor storage device according to claim 1, wherein:

the BGA terminal includes a plurality of terminals located in a prescribed pattern;

a part of the plurality of terminals is used for interfacing with the external system or for supplying a power supply; and

another part of the plurality of terminals includes dummy terminals which are not used for interfacing or providing a power supply.

5. A method for producing a semiconductor storage device, the semiconductor storage device including:

a controller package having a BGA terminal on a bottom surface thereof; and

one or a plurality of memory packages each including a plurality of semiconductor storage elements and mounted on the controller package;

wherein the controller package includes;

a bottom substrate having the BGA terminal on a bottom surface thereof;

a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and

a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC, the controller providing an interface with an external system via the BGA terminal and controlling a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements;

wherein a memory terminal pattern for mounting the one or plurality of memory packages thereon is formed on a top surface of the controller package, the memory terminal pattern being connected to the controller;

the method for producing the semiconductor storage device comprising stacking and connecting the controller package selected as being good by a first test and the one or plurality of memory packages selected as being good by a second test.