LOW TEMPERATURE DRIFT VOLTAGE REFERENCE CIRCUIT
First Claim
1. A voltage reference circuit, comprising:
- a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground, wherein the first depletion-mode PMOS transistor has shorted gate and source;
a second depletion-mode PMOS transistor having a source coupled to the gate of the first enhancement PMOS transistor at a first node, the second depletion-mode PMOS transistor also having a gate coupled to a drain of the first enhancement-mode PMOS transistor at a second node, forming a feedback circuit;
a first resistive device coupled between the voltage supply and the first node;
a second resistive device, which has one end coupled to the drain of the second depletion-mode PMOS transistor at a third node and has the other end coupled to the ground; and
a bias circuit coupled to a gate of the first enhancement-mode NMOS transistor;
wherein the first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region, and a first reference voltage between the voltage supply and the first node is independent of the magnitude of the voltage supply.
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Accused Products
Abstract
A voltage reference circuit includes a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground. A second depletion-mode PMOS transistor is coupled to the first enhancement PMOS transistor to form a feedback circuit. A first resistive device is coupled between the voltage supply and the second depletion-mode PMOS transistor, and a second resistive device is coupled between the second depletion-mode PMOS transistor and the ground. A bias circuit is coupled to a gate of the first enhancement-mode NMOS transistor. The first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region. A first reference voltage across the first resistor and a second reference voltage across the second resistor are configured to be independent of the magnitude of the voltage supply and have low temperature drift.
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Citations
21 Claims
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1. A voltage reference circuit, comprising:
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a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground, wherein the first depletion-mode PMOS transistor has shorted gate and source; a second depletion-mode PMOS transistor having a source coupled to the gate of the first enhancement PMOS transistor at a first node, the second depletion-mode PMOS transistor also having a gate coupled to a drain of the first enhancement-mode PMOS transistor at a second node, forming a feedback circuit; a first resistive device coupled between the voltage supply and the first node; a second resistive device, which has one end coupled to the drain of the second depletion-mode PMOS transistor at a third node and has the other end coupled to the ground; and a bias circuit coupled to a gate of the first enhancement-mode NMOS transistor; wherein the first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region, and a first reference voltage between the voltage supply and the first node is independent of the magnitude of the voltage supply. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A voltage reference circuit, comprising:
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a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground, wherein; the first enhancement-mode PMOS transistor has a source coupled to the voltage supply; the first enhancement-mode NMOS transistor has a drain coupled to the drain of the first enhancement-mode PMOS transistor; the first depletion-mode PMOS transistor M3 has a source and a gate coupled to a source of the first enhancement-mode NMOS transistor; a second depletion-mode PMOS transistor having a source coupled to the gate of the first enhancement PMOS transistor Ml at a first node, the second depletion-mode PMOS transistor also having a gate coupled to a drain of the first enhancement-mode PMOS transistor at a second node, forming a feedback loop; a first resistive device coupled between the voltage supply and the source of the second depletion-mode PMOS transistor; a second resistive device, which has one end coupled to the drain of the second depletion-mode PMOS transistor M7 at a third node and has the other end coupled to the ground; the first depletion-mode PMOS transistor coupled to the first enhancement-mode NMOS transistor at a fourth node; and a bias circuit coupled to a gate of the first enhancement-mode NMOS transistor M2 at a fifth node, the bias circuit configured to maintain the first depletion-mode PMOS transistor to operate in saturation region, wherein the bias circuit includes a third depletion-mode PMOS transistor, a second enhancement-mode NMOS transistor, and a third enhancement-mode NMOS transistor coupled in series between the voltage supply and the ground, wherein; the third depletion-mode PMOS transistor has a source and a gate coupled to the voltage supply; the second enhancement-mode NMOS transistor has a gate and a drain coupled the drain of the third depletion-mode PMOS transistor and coupled to the gate of the first enhancement-mode MOS transistor and at a fifth node; and the third enhancement-mode NMOS transistor has a drain and a gate coupled to a source of third enhancement-mode NMOS transistor and the ground GND at a sixth node; wherein the voltage reference circuit is configured to provide a first reference voltage between the voltage supply at the first node, and a second reference voltage between the third node and the ground, wherein the first and the second reference voltage are independent of the voltage supply, and a temperature coefficient of the first reference voltage is within a preset limit. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A voltage reference circuit, comprising:
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a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground; a first resistive device, a feedback device, and a second resistive device coupled in series between the voltage supply and the ground, wherein the feedback device is coupled to the first enhancement PMOS transistor to form a feedback circuit; and a bias circuit coupled to a gate of the first enhancement-mode NMOS transistor; wherein the first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region; wherein a first reference voltage across the first resistive device and a second reference voltage across the second resistive device are configured to be independent of the magnitude of the voltage supply and have temperature coefficients within a preset limit. - View Dependent Claims (18, 19, 20, 21)
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Specification