LEVEL-TWO ENCRYPTION ASSOCIATED WITH INDIVIDUAL PRIVACY AND PUBLIC SAFETY PROTECTION VIA DOUBLE ENCRYPTED LOCK BOX

• US 20140105388A1
• Filed: 10/30/2012
• Published: 04/17/2014
• Est. Priority Date: 10/16/2012
• Status: Abandoned Application

• Current Assignee: Elwha LLC (Intellectual Ventures LLC)
• Original Assignee: Elwha LLC (Intellectual Ventures LLC)
• Inventors: Jung, Edward K.Y., Levien, Royce A., Lord, Richard T., Lord, Robert W., Malamud, Mark A.
• Application Number:
  US13/664,265
• Publication Number:
  US 20140105388A1
• Time in Patent Office: Days
• US Class Current: 380/45
• CPC Class Codes: H04L 2209/04 Masking or blinding
• CPC Class Codes: H04L 9/08 Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords network architectures or network communication protocols for supporting key management in a packet data network H04L63/06
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04N 7/1675 Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58

Abstract

A method substantially as shown and described the detailed description and/or drawings and/or elsewhere herein. A device substantially as shown and described the detailed description and/or drawings and/or elsewhere herein.

Claims

1-41. -41. (canceled)

42. A machine comprising:

level-two encryption circuitry adapted to interface with level-one encryption circuitry;

said level-two encryption circuitry adapted to interface with level-two key-pair generation automation;

said level-two encryption circuitry associated with level-two blind encryption circuitry; and

said level-two encryption circuitry adapted to interface with a pre-event repository.

43. The machine of claim 42, wherein level-one encryption circuitry comprises:

said level-one encryption circuitry adapted to interface with level-one key-pair generation automation.

44. The machine of claim 43, wherein level-one encryption circuitry adapted to interface with level-one key-pair generation automation comprises:

said level-one encryption circuitry adapted to receive from the level-one key-pair generation automation a level-one encryption key whose decryption key is inaccessible by said level-one encryption circuitry.

45. The machine of claim 42, wherein level-two encryption circuitry adapted to interface with level-one encryption circuitry comprises:

said level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output of a surveillance device.

46. The machine of claim 45, wherein level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output of a surveillance device comprises:

said level-two encryption circuitry adapted to receive from said level-one encryption circuitry a level-one encrypted output of a surveillance device that is associated with data that cannot be practicably decrypted by the level-one encryption circuitry.

47. The machine of claim 45, wherein level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output of a surveillance device comprises:

said level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output of a surveillance device that is associated with data that has been encrypted by the level-one encryption circuitry with an encryption key the unlocking decryption key of which the level-one encryption circuitry has no knowledge.

48. The machine of claim 45, wherein level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output of a surveillance device comprises:

said level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output of at least one of an image surveillance device, an audio surveillance device, a motion surveillance device, or a tactile surveillance device.

49. The machine of claim 45, wherein level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output of a surveillance device comprises:

said level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output that is associated with level-one key-pair generation automation.

50. The machine of claim 49, wherein level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output that is associated with level-one key-pair generation automation comprises:

said level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output that is associated with a decryption key generated by level-one key-pair generation automation.

51. The machine of claim 49, wherein level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output that is associated with level-one key-pair generation automation comprises:

said level-two encryption circuitry adapted to receive from the level-one encryption circuitry a level-one encrypted output that is associated with a key-pair designator generated by level-one key-pair generation automation.

52. The machine of claim 42, wherein level-two encryption circuitry associated with level-two blind encryption circuitry comprises:

said level-two blind encryption circuitry adapted to interface with level-two key-pair designator reception circuitry.

53. The machine of claim 52, wherein level-two key-pair designator reception circuitry comprises:

said level-two key-pair designator reception circuitry adapted to store/utilize a level-two encryption key generated by the level-two key-pair generation automation.

54. The machine of claim 52, wherein level-two key-pair designator reception circuitry comprises:

said level-two key-pair designator reception circuitry adapted to store/utilize a unique level-two key-pair designator generated by the level-two key-pair generation automation.

55. The machine of claim 42, wherein level-two encryption circuitry comprises:

level-two encrypted transmission circuitry adapted to interface with level-two surveillance device identifier circuitry.

56. The machine of claim 42, wherein level-two encryption circuitry comprises:

level-two encrypted transmission circuitry coupled with level-two surveillance device identifier circuitry.

57. The machine of claim 56, wherein level-two surveillance device identifier circuitry comprises:

said level-two surveillance device identifier circuitry adapted to receive an encrypted surveillance device identifier.

58. The machine of claim 42, wherein level-two encryption circuitry associated with level-two blind encryption circuitry comprises:

said level-two blind encryption circuitry adapted to interface with level-two key-pair generation automation.

59. The machine of claim 58, wherein level-two blind encryption circuitry adapted to interface with level-two key-pair generation automation comprises:

said level-two blind encryption circuitry adapted to receive from the level-two key-pair generation automation a level-two encryption key whose decryption key is inaccessible by a level-two encryption entity.

60. The machine of claim 59, wherein level-two blind encryption circuitry adapted to receive from the level-two key-pair generation automation a level-two encryption key whose decryption key is inaccessible by a level-two encryption entity comprises:

said level-two blind encryption circuitry adapted to receive a level-two key pair designator from the level-two key-pair generation automation.

61. The machine of claim 60, wherein level-two blind encryption circuitry adapted to receive a level-two key pair designator from the level-two key-pair generation automation comprises:

said level-two blind encryption circuitry adapted to receive from level-two key pair designator reception circuitry a level-two key pair designator in the form of a level-two encryption key that may thereafter function as the level-two key-pair designator.

62. The machine of Claim of 60, wherein level-two blind encryption circuitry adapted to receive a level-two key pair designator from the level-two key-pair generation automation comprises:

said level-two blind encryption circuitry constructed to encrypt at least a part of a level-one encrypted output of the surveillance device into a form such that a level-two encrypted output of the surveillance device is substantially unusable absent combination with other information not present in the level-two encrypted output of the surveillance device.

63. The machine of claim 62, wherein level-two blind encryption circuitry constructed to encrypt at least a part of a level-one encrypted output of the surveillance device into a form such that a level-two encrypted output of the surveillance device is substantially unusable absent combination with other information not present in the level-two encrypted output of the surveillance device comprises:

said level-two blind encryption circuitry adapted to receive from level-two key pair designator reception circuitry a level-two encryption key whose decryption key is inaccessible by a level-two encryption entity, the level-two key pair designator reception circuitry adapted to receive the level-two encryption key whose decryption key is inaccessible by the level-two encryption entity from level-two key-pair generation automation.

64. The machine of claim 62, wherein level-two blind encryption circuitry constructed to encrypt at least a part of a level-one encrypted output of the surveillance device into a form such that a level-two encrypted output of the surveillance device is substantially unusable absent combination with other information not present in the level-two encrypted output of the surveillance device comprises:

said level-two blind encryption circuitry adapted to interface with level-two key-pair generation automation to receive a level-two key pair designator.

65. The machine of claim 42, wherein level-two encryption circuitry associated with level-two blind encryption circuitry comprises:

said level-two blind encryption circuitry adapted to interface with level-two key-pair generation automation to receive a level-two key pair designator in the form of a level-two encryption key that may thereafter function as the level-two key-pair designator.

66. The machine of claim 42, wherein level-two encryption circuitry adapted to interface with a pre-event repository comprises:

said level-two encryption circuitry adapted to interface with the pre-event repository such that a level-two encrypted output of a surveillance device may be transmitted.

67. The machine of claim 66, wherein level-two encryption circuitry adapted to interface with the pre-event repository such that a level-two encrypted output of a surveillance device may be transmitted comprises:

said level-two encryption circuitry adapted to interface with the pre-event repository such that the level-two encrypted output of the surveillance device in conjunction with a surveillance device identifier may be transmitted.

68. The machine of claim 67, wherein level-two encryption circuitry adapted to interface with the pre-event repository such that the level-two encrypted output of the surveillance device in conjunction with a surveillance device identifier may be transmitted comprises:

said level-two encryption circuitry adapted to interface with the pre-event repository such that the level-two encrypted output of the surveillance device in conjunction with an encrypted version of the surveillance device identifier may be transmitted.

69. The machine of claim 68, wherein level-two encryption circuitry adapted to interface with the pre-event repository such that the level-two encrypted output of the surveillance device in conjunction with an encrypted version of the surveillance device identifier may be transmitted comprises:

level-two surveillance device identifier circuitry adapted to interface with the level-one encryption circuitry to receive an encrypted version of the surveillance device identifier.

70. The machine of claim 68, wherein level-two encryption circuitry adapted to interface with the pre-event repository such that the level-two encrypted output of the surveillance device in conjunction with an encrypted version of the surveillance device identifier may be transmitted comprises:

said level-two encryption circuitry adapted to interface with level-one encryption circuitry to;

receive an encryption of at least a part of a version of the surveillance device identifier that was encrypted with a name-obscuring encryption key whose decryption key is inaccessible by a level-one encryption entity; and

transmit an encrypted version of the surveillance device identifier to the pre-event repository.

71. The machine of claim 42, wherein level-two encryption circuitry comprises:

said level-two blind encryption circuitry constructed with level-two encrypted transmission circuitry adapted to interface with the pre-event repository to transmit a level-two encrypted output of the surveillance device to the pre-event repository.

72. The machine of claim 42, wherein the machine further comprises:

at least one of static or sequenced hardware elements.

73. The machine of claim 42, wherein the machine further comprises:

at least one ordered matter element.

74. The machine of claim 73, wherein at least one ordered matter element further comprises:

at least one logic gate.

75. The machine of claim 74, wherein at least one logic gate further comprises:

at least one physical device that may be driven to change physical state in order to create a physical reality of Boolean logic.

76. The machine of claim 73, wherein at least one ordered matter element further comprises:

at least one logic circuit.

77. The machine of claim 76, wherein at least one logic circuit further comprises:

one or more physical logic gates that may be arranged to form physical logic circuits that may be driven to create a physical reality of one or more logical functions.

78. The machine of claim 77, wherein one or more physical logic gates that may be arranged to form physical logic circuits that may be driven to create a physical reality of one or more logical functions further comprises:

at least one of a multiplexer, a latch, or a register.

79. The machine of claim 77, wherein one or more physical logic gates that may be arranged to form physical logic circuits that may be driven to create a physical reality of one or more logical functions further comprises:

at least one of an arithmetic logic unit, a computer memory, or a bridge.

80. The machine of claim 77, wherein one or more physical logic gates that may be arranged to form physical logic circuits that may be driven to create a physical reality of one or more logical functions further comprises:

at least one central processing unit.

81. The machine of claim 77, wherein one or more physical logic gates that may be arranged to form physical logic circuits that may be driven to create a physical reality of one or more logical functions further comprises:

at least one configuration responsive to a defined Instruction Set Architecture.

82. The machine of claim 77, wherein one or more physical logic gates that may be arranged to form physical logic circuits that may be driven to create a physical reality of one or more logical functions further comprises:

at least one circuit constructed to convert a machine language instruction to at least one of a voltage control, a timing control, a selection control, or an activation control.

83. The machine of claim 73, wherein at least one ordered matter element further comprises:

at least one integrated electrical circuit.

84. The machine of claim 73, wherein at least one ordered matter element further comprises:

at least one application specific integrated electrical circuit.

85. The machine of claim 73, wherein at least one ordered matter element further comprises:

at least one general purpose computer configured by a computer program.

86. The machine of claim 85, wherein at least one general purpose computer configured by a computer program further comprises:

at least one general purpose computer processor operably coupled with a hardware memory having at least a part of the computer program.

87. A machine comprising:

level-two encryption circuitry adapted to interface with a surveillance device through level-one encryption circuitry;

said level-two encryption circuitry adapted to interface with level-two key-pair automation associated with level-two blind encryption circuitry; and

said level-two encryption circuitry adapted to interface with a pre-event repository.

88. A machine comprising:

level-two encryption circuitry adapted to interface with a surveillance device through level-one encryption circuitry; and

said level-two encryption circuitry adapted to interface with level-two key-pair automation associated with level-two blind encryption circuitry.