Method of Determining Electromigration (EM) Lifetimes and Lifetime Criteria

• US 20140109030A1
• Filed: 07/31/2013
• Published: 04/17/2014
• Est. Priority Date: 10/15/2012
• Status: Abandoned Application

• Current Assignee: Intermolecular Incorporated
• Original Assignee: Intermolecular Incorporated
• Inventors: Lee, Mankoo, Chiang, Tony P., Pramanik, Dipankar
• Application Number:
  US13/956,220
• Publication Number:
  US 20140109030A1
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G01R 31/2848 using simulation
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Methods are described for performing detailed Technology Computer Aided Design (TCAD) simulations of electromigration (EM) failure in a standard test structure suitable for the simulation of integrated circuit (IC) conductive interconnects. Methods are described for performing these simulation so as to extract from the results of these simulations criteria substantially underlying the EM lifetime of interconnects, thereby permitting rapid diagnosis of potential sites of EM failure early in the IC design and fabrication process, and thereby allowing more rapid development of reliable ICs robust against EM failure. Specific results for EM failure criteria in Cu interconnects are also presented.

Claims

1. A method for improving the design of integrated circuits (ICs) by improving resistance to electromigration failure, the method comprising:

for a candidate IC design, varying current density j and interconnect length L through a range of values for each interconnect and, at each set of values, determining a lifetime until electromigration failure with a Technology Computer Aided Design (TCAD) computer simulation; and

,

constructing one or more charts of lifetime as functions of j and L; and

,

extracting from these one or more charts, one or more regions of safety from electromigration failure, one or more electromigration failure regions, and one or more aware regions of neither safety nor failure; and

,

correlating the safety, failure, and aware regions with ranges of the product jL; and

,

determining susceptibility to electromigration failure for interconnects within the integrated circuit by computing the product jL for each interconnect and determining if it falls in a safe, failure, or aware region, and

redesigning the IC for those interconnects in the failure region so as to move the jL product out of the failure region.

2. A method as in claim 1 wherein the TCAD computer simulation is performed on a test structure including both vias and interconnects.

3. A method as in claim 2 wherein the TCAD computer simulation is performed on a test structure capable of simulating both forward and reverse current flows.

4. A method as in claim 1 wherein the TCAD computer simulation is performed on a test structure compatible with 2×

nm Back End Of Line technology.

5. A method as in claim 3 wherein the test structure has one or more marginal conductor line extensions from the end of at least one via, simulating thereby at least one reservoir for vacancies.

6. A method as in claim 3 wherein the test structure includes one or more barrier liners connected so as to permit measurement of the resistance slope following electromigration failure.

7. A method as in claim 6 wherein the one or more barrier layers contain Ta, Ru and/or Co.

8. A method as in claim 7 wherein the one or more barrier layers include TaN.

9. A method for the determination of electromigration performance of Cu interconnect sites within an integrated circuit, the method comprising:

computing the product of current density, j, and interconnect length, L, for the interconnects within the integrated circuit; and

,

identifying interconnects prone to electromigration failure as those interconnects for which the jL product is greater than about 9,000 amps/cm.

10. A method as in claim 9 further comprising:

identifying interconnects safe from electromigration failure as those interconnects for which the jL product is less than about 2,000 amps/cm.

11. A method for improving the design of an integrated circuit (IC) by improving the electromigration failure lifetime (t_f) wherein the IC contains at least one interconnect and barrier layer, the method comprising:

a) performing a sensitivity analyses on t_f with a sequence of Technology Computer Aided Design (TCAD) computer simulations for material properties of the interconnect and barrier layer, thereby determining the sensitivity of t_f to the material properties wherein the sensitivity analysis comprises;

a-1) choosing a value for initial vacancy concentration (IVC) as the estimated value of the oxygen concentration directly beneath the barrier layer; and

,

a-2) choosing a value for void formation density (VFD) as the estimated value of the metal segregation concentration; and

,

a-4) performing a TCAD sensitivity analysis on t_f to determine the sensitivity of t_f to IVC, VFD; and

,

b) setting Gibbs free energy parameter values for the surface energy density (SED) and grain boundary surface energy density of voids (GED); and

,

c) determining with TCAD computer simulation the dependence of t_f on the length L of a particular interconnect under consideration, and determining the range of material properties relatively safe from electromigration failure, by the following steps (c-1)-(c-4);

c-1) determining t_f for a sequence of L values and for a sequence of current densities (j); and

,

c-2) determining safe and failure regions from the results of (c-1) and an aware region between the safe region and the failure region; and

,

c-3) determining values of the jL product at the boundaries of the safe and failure regions; and

,

c-4) performing further TCAD computer simulations in the t_f aware region; and

,

d) determining the dependence of t_f on temperature (T) to determine safe temperature regions by the following steps (d-1)-(d-3);

d-1) determining activation energies associated with the diffusion process from an Arrhenius plot of t_f under forward and reverse current flows; and

,

d-2) determining the temperature dependence of t_f under the condition that the void concentration (C_void) is substantially the same as the vacancy concentration (C_v); and

,

d-3) determining the temperature dependence of the Blech threshold (jL)_c in the aware region; and

,

e) comparing the t_f values determined herein with measured values of t_f; and

,

f) returning to step (b) if the value t_f values determined herein differ from the measured t_f values by more than a desired amount, otherwise terminate the method and record the material property values that produced adequate agreement; and

,

g) employing the material properties producing good agreement between computed t_f and measured t_f, identifying interconnects susceptible to electromigration failure; and

,

h) redesigning the IC so as to increase t_f for those interconnects susceptible to electromigration failure, thereby increasing the robustness of the IC.

12. A method as in claim 11 wherein the following parameters are used to simulate Cu interconnects:

VFD=8.5×

10²² atoms/cm³,

IVC=1% VFD,

SED=1.7×

10<sup>−

4</sup> Joules (J_o)/cm², and

GED=6.3×

10<sup>−

5</sup> J_o/cm².

13. A method as in claim 11 wherein the at least one interconnect includes a Cu alloy interconnect.

14. A method as in claim 11 wherein the IVC includes a sum of all initial vacancies that can arise in a Cu-alloy with dopants.

15. A method as in claim 14 wherein the IVC includes a sum of all initial vacancies that can arise in a Cu-alloy from chemical processes involving oxygen.

16. A method as in claim 13 wherein the at least one Cu alloy interconnect is Cu-aluminum (Cu—

Al) and/or Cu-manganese (Cu—

Mn).

17. A method as in claim 16 wherein, when Cu—

Al is present, IVC is adjusted to account for reactions of Al with oxygen to form Al₂O₃, thereby increasing IVC.

18. A method as in claim 11 wherein a full TCAD simulation is performed for IVC for each Back End Of Line process condition under consideration.

19. A method as in claim 11 wherein the activation energy associated with Cu diffusion extracted from an Arrhenius plot is about 0.9 eV.

20. A method as in claim 11 wherein t_f is determined by the time until an increase in resistance of about 10% occurs.