METHODS AND SYSTEMS FOR INTEGRATED CIRCUIT C4 BALL PLACEMENT

• US 20140109032A1
• Filed: 12/12/2013
• Published: 04/17/2014
• Est. Priority Date: 07/13/2011
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Guthaus, Matthew, Logan, Sheldon
• Granted Patent: US 8,966,427 B2
• Time in Patent Office: Days
• US Class Current: 716/119
• CPC Class Codes: G06F 2111/10 Numerical modelling
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling.

Claims

1. A method of laying out C4 ball placements, comprising using a computer to perform the following steps:

(i) calculating the optimal position of C4 solder balls on a chip using a quadratic optimization technique;

(ii) producing a grid map of all possible C4 ball locations based on the minimum pitch distance for the C4 balls and the length and width of the chip;

(iii) generating a temperature map from the produced grid map;

(iv) determining the thermal stress on a C4 ball at each possible C4 ball location in the grid maps by using the temperature map;

(v) calculating a thermal failure rate for each possible C4 ball location based on thermal stresses, creep rates, and number of cycles to failure rates for the C4 balls;

(vi) producing a reduced grid map by removing all possible C4 ball locations from the grid map that have a higher thermal failure rate than a predetermined threshold;

(vii) legalizing possible C4 ball locations in the reduced grid map so as to generate bin entries;

(viii) sorting possible C4 ball locations based on bin entries; and

(ix) locating a set of C4 ball locations within the reduced grid map using bin entries such that overlaps between other C4 ball locations and removed C4 ball locations are avoided.

2. The method according to claim 1, wherein the step of calculating the optimal position of C4 solder balls includes receiving a device netlist having a number of electrical contacts and solving further includes solving the following quadratic equation:

3. The method according to claim 1, wherein the step of producing a reduced grid map is performed by receiving a minimum number of cycles to failure for all balls in the design and to removing all possible ball locations with a value below the received number of cycles.

4. The method according to claim 1, wherein the step of producing a reduced grid map is performed by receiving a number (N) of possible ball locations that will not be used and removing N ball locations having the lowest number of cycles to failure.

5. The method according to claim 1, wherein the step of legalizing possible C4 ball locations is performed by assigning C4 balls to a subset of the optimal ball positions, wherein an optimal ball is placed in that subset if the optimal ball position is in the reduced grid map and if the optimal ball positions avoids overlap with other C4 balls and the ball locations not in the reduced grid map.

6-8. -8. (canceled)

9. A system for laying out C4 ball placements, comprising using a computer to perform the following steps:

(i) inputting into the computer specifications regarding the length and width of a semiconductor device to receive C4 balls;

(ii) inputting into the computer a device netlist having a number of electrical contacts to be implemented;

(iii) inputting into the computer a minimum number of cycles to failure for C4 solder balls;

(iv) operating the computer to calculate the optimal position of C4 solder balls using a quadratic optimization technique;

(v) generating a grid map of all possible C4 ball locations based on the minimum pitch distance for the C4 balls and the length and width of the chip;

(vi) generating a temperature map from the produced grid map;

(vii) operating the computer to calculate the thermal stress on a C4 ball at each possible C4 ball location in the grid maps by using the temperature map;

(viii) operating the computer to calculate a thermal failure rate for each possible C4 ball location based on thermal stresses, creep rates, and number of cycles to failure rates for the C4 balls;

(ix) generating a reduced grid map by removing all possible C4 ball locations from the grid map that have a higher thermal failure rate than a predetermined threshold;

(x) computationally legalizing possible C4 ball locations in the reduced grid map so as to generate bin entries;

(xi) sorting possible C4 ball locations based on bin entries; and

(xii) using the computer to locate a set of C4 ball locations on the semiconductor device and within the reduced grid map using bin entries such that overlaps between other C4 ball locations and removed C4 ball locations are avoided.

10. The system according to claim 9, wherein the step of calculating the optimal position of C4 solder balls includes having a computer solve the following quadratic equation:

11. The system according to claim 9, wherein producing a reduced grid map is performed by removing all possible ball locations with a value below the received number of cycles.

12. The system according to claim 9, wherein computationally producing a reduced grid map is performed by inputting into a computer a number (N) of possible ball locations that will not be used and then removing N ball locations having the lowest number of cycles to failure.

13. The system according to claim 9, wherein computationally legalizing possible C4 ball locations is performed by computationally assigning C4 balls to a subset of the optimal ball positions, wherein an optimal ball is placed in that subset if the optimal ball position is in the reduced grid map and if the optimal ball positions avoids overlap with other C4 balls and the ball locations not in the reduced grid map.

14-16. -16. (canceled)