Time Monitoring in a Processing Element and Use

• US 20140109096A1
• Filed: 08/27/2013
• Published: 04/17/2014
• Est. Priority Date: 10/15/2012
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Chandhoke, Sundeep
• Granted Patent: US 9,304,810 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/3006 where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems multiprogramming arrangements G06F9/46; allocation of resources G06F9/50
• CPC Class Codes: G06F 11/3051 Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs verification or detection of system hardware configuration G06F11/2247
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains. The thread suspend/resume logic block included in the processing element may be invoked by the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread

Claims

1. A system comprising:

a processing element, comprising;

a clock;

a thread suspend/resume logic block, configured to suspend execution of a thread in response to a received suspend thread instruction; and

a time monitor circuit (TMC), wherein the TMC is configured to;

receive an indication of a wakeup time;

monitor time via the clock until the wakeup time obtains; and

invoke the thread suspend/resume logic block to resume execution of the thread in response to the wakeup time obtaining

2. The system of claim 1, wherein the indication of the wakeup time is an absolute time.

3. The system of claim 1, wherein the indication of the wakeup time is a relative time.

4. The system of claim 1, wherein the TMC is further configured to discipline the clock via an external time source.

5. The system of claim 4, wherein to discipline the clock via an external time source, the TMC is configured to discipline the clock using a global time provided by software.

6. The system of claim 5, further comprising:

a local reference clock, coupled to the processing element and to a peripheral device, wherein the peripheral device is configured to provide the global time to the processing element;

wherein to provide the global time, the software is executable to retrieve a local reference time from the local reference clock that corresponds to the global time, and provide the global time and the local reference time to the processing element;

wherein to discipline the clock, the TMC is configured to retrieve a subsequent local reference time from the local reference clock, and adjust the global time based on a difference between the subsequent local reference time and the local reference time, thereby compensating for latency due to the provision of the global time by the software.

7. The system of claim 6, wherein the local reference clock is connected directly to the processing element and the peripheral device.

8. The system of claim 5, further comprising:

a local reference clock, coupled to the processing element and to a network interface controller (NIC), wherein the NIC is configured to provide the global time to the processing element;

wherein to provide the global time, the software is executable to retrieve a local reference time from the local reference clock that corresponds to the global time, and provide the global time and the local reference time to the processing element;

wherein to discipline the clock, the TMC is configured to retrieve a subsequent local reference time from the local reference clock, and adjust the global time based on a difference between the subsequent local reference time and the local reference time, thereby compensating for latency due to the provision of the global time by the software.

9. The system of claim 8, wherein the local reference clock is connected directly to the processing element and the peripheral device.

10. The system of claim 4, wherein the external time source comprises an external hardware signal, wherein the external hardware signal comprises an epoch and a clock signal.

11. A method, comprising:

receiving an indication of a wakeup time to a time monitoring circuit (TMC) comprised in a processing element;

suspending execution of a thread via a thread suspend/resume logic block comprised in the processing element in response to a received suspend thread instruction;

monitoring time, via the TMC using a clock comprised in the processing element, until the wakeup time obtains; and

invoking the thread suspend/resume logic block via the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread.

12. The method of claim 11, wherein the indication of the wakeup time is an absolute time.

13. The method of claim 11, wherein the indication of the wakeup time is a relative time.

14. The method of claim 11, further comprising:

disciplining the clock, via the TMC via an external time source.

15. The method of claim 14, wherein a global time provided by software is used to perform said disciplining.

16. The method of claim 15, further comprising:

providing the global time to the processing element via a peripheral device, wherein a local reference clock is coupled to the processing element and to the peripheral device;

retrieving, via software, a local reference time from the local reference clock that corresponds to the global time to perform said providing;

wherein said disciplining comprises;

retrieving, via the TMC, a subsequent local reference time from the local reference clock; and

adjusting, via the TMC, the global time based on a difference between the subsequent local reference time and the local reference time, thereby compensating for latency due to the provision of the global time by software.

17. The method of claim 16, wherein the local reference clock is connected directly to the processing element and the peripheral device.

18. The method of claim 15, further comprising:

providing a global time to the processing element via a network interface controller (NIC), wherein a local reference clock is coupled to the processing element and the NIC;

retrieving, via software, a local reference time from the local reference clock that corresponds to the global time to perform said providing;

wherein said disciplining comprises;

retrieving, via the TMC, a subsequent local reference time from the local reference clock; and

adjusting, via the TMC, the global time based on a difference between the subsequent local reference time and the local reference time, thereby compensating for latency due to the provision of the global time by software.

19. The method of claim 18, wherein the local reference clock is connected directly to the processing element and the peripheral device.

20. The method of claim 15, wherein the external time source comprises an external hardware signal, wherein the external hardware signal comprises an epoch and a clock signal.