TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF

• US 20140110777A1
• Filed: 10/18/2012
• Published: 04/24/2014
• Est. Priority Date: 10/18/2012
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: PENG, Chun-Hong, LAI, Yu-Hsi
• Application Number:
  US13/654,432
• Publication Number:
  US 20140110777A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.

Claims

1. A trench gate metal oxide semiconductor field effect transistor, comprising:

a substrate having a trench formed therein, wherein the trench is extended downwardly from a surface of the substrate; and

a gate comprising an insertion portion and a symmetrical protrusion portion, wherein the insertion portion is embedded in the trench, and the symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.

2. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the symmetrical protrusion portion is wider than the trench.

3. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the gate is a T-shaped gate, which is symmetrical with respect to a central line of the trench.

4. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the trench has a width smaller than or equal to 0.8 μ

m and a depth of about 1.6 μ

m.

5. The trench gate metal oxide semiconductor field effect transistor according to claim 1, further comprising:

a dielectric material layer disposed over the surface of the substrate and the gate; and

at least one contact plug penetrated through the dielectric material layer and electrically contacted with the symmetrical protrusion portion of the gate.

6. The trench gate metal oxide semiconductor field effect transistor according to claim 1, further comprising:

a first-conductive doped region formed in the substrate;

a second-conductive doped region formed in the substrate, wherein a P/N junction is formed between the first-conductive doped region and the second-conductive doped region, the trench is extended downwardly from the surface of the trench, penetrated through the first-conductive doped region and the P/N junction, and inserted into the second-conductive doped region;

a gate dielectric layer formed on a sidewall of the trench; and

a source region formed in the substrate and located beside the gate dielectric layer.

7. The trench gate metal oxide semiconductor field effect transistor according to claim 6, wherein the first-conductive doped region is a P-type body region, and the second-conductive doped region is an N-type well region.

8. The trench gate metal oxide semiconductor field effect transistor according to claim 6, further comprising an N-type buried layer, which is disposed under the second-conductive doped region.

9. The trench gate metal oxide semiconductor field effect transistor according to claim 6, wherein the source region is an N-type well region, and the source region is extended from the surface of the substrate into the first-conductive doped region.

10. A method for fabricating a trench gate metal oxide semiconductor field effect transistor, the method comprising steps of:

providing a substrate;

forming a hard mask layer on the substrate;

performing an etching process to remove a part of the hard mask layer and forming a trench in the substrate;

performing an etching back process to remove a part of the hard mask layer;

forming a conductive layer on the hard mask layer, and filling the polysilicon layer into the trench; and

performing a planarization process to remove the conductive layer by using the hard mask layer as a stop layer.

11. The method according to claim 10, wherein before the hard mask layer is formed, the method further comprises a step of forming a pad silicon oxide layer on the substrate.

12. The method according to claim 10, wherein after the hard mask layer is formed, the method further comprises a step of forming a sacrificial layer on the hard mask layer.

13. The method according to claim 10, wherein before the conductive layer is formed, the method further comprises a step of forming a gate dielectric layer on a sidewall of the trench by a thermal oxidation process.

14. The method according to claim 10, wherein the hard mask layer is a silicon oxide layer or a silicon nitride layer.